[Libre-silicon-devel] Update: RCL cross verification
hsank at posteo.de
Tue Jul 9 14:59:41 CEST 2019
On 7/9/19 2:39 PM, David Lanzendörfer wrote:
> Hi everyone
> So I've had a mail exchange and we can go through our recent status together
> with the engineers at RCL, as soon as we're done cleaning up everything.
> a) We've gotta rework PearlRiver, so that it's in accordance with the new
> design rules which arose from the R&D.
> Mainly: Contact holes should all have the same size because the dry etching
> time is varying with the area of the contact hole.
> So the yield goes into the basement when the vias/contacts in the oxide all
> have different dimensions.
Do we already have the updated scmos.tech file for Magic somewhere?
I like to evaluate the new (minimum) cell layout with right DRC rules.
> b) Also I'm right now cleaning up the documentation for the process so that it
> reflects what I've actually done the past year in the lab.
Great! Go ahead :-)
> c) After we're done with it, we'll do some legal stuff and can most likely
> make a test run.
Hope, we are soon ready to show next GDS2 for the PearlRiver.
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