[Libre-silicon-devel] PMOS characteristization

Éger Ferenc eegerferenc at gmail.com
Sat Jul 13 22:32:31 CEST 2019


Hello Everyone,

Today I figured out how to extract the drain current of the "real" PMOS
from the currently available "leaky" measurements. The process is:

1. Take "thermally_compensated". 2. Compute the slope of the curve (i.e.
leakage conductance) by averaging dY/dX between -0.5 and 0V (where "real")
drain current is expected to be zero. 3. Based on that, calculate the D-G
leakage current (linear resistive case). 4. Subtract the leakage from the
measurement data.

[image: image.png]

The results show clearly a quadratic Id-Vgs behavior and a Vth around 0.6V.
The spreadsheet containing the calculation is attached.

According to David, this was taken at a PMOS L10/W10 cell. Unfortunately,
for the NMOS results, the instrument went off-scale around Vgs=0V, so the
neccessary fix points cannot be acquired.

Regards,
Ferenc
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://list.libresilicon.com/pipermail/libresilicon-developers/attachments/20190713/ab917edc/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: image.png
Type: image/png
Size: 5941 bytes
Desc: not available
URL: <http://list.libresilicon.com/pipermail/libresilicon-developers/attachments/20190713/ab917edc/attachment.png>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: thermally_compensated.ods
Type: application/vnd.oasis.opendocument.spreadsheet
Size: 78159 bytes
Desc: not available
URL: <http://list.libresilicon.com/pipermail/libresilicon-developers/attachments/20190713/ab917edc/attachment.ods>


More information about the Libresilicon-developers mailing list