leviathan at libresilicon.com
Sat Jun 29 09:54:53 CEST 2019
So the test run for increased polysilicon thickness in order to fix the
leakage has been successful, as least from a visual point of view.
The nitride spacer walls are now visible under the microscope.
It just seems as if some idiot has put the wrong sputter source into the
Titanium compartment for the NSC3000 which wouldn't have been a problem if the
Varian sputterer wouldn't have spontaneously broken again on Thursday.
So now, as with mystery meals, I have no idea what exactly is on those wafers.
It's kind of reasonable that the film might be transparent, because of a
different uniformity, but then again, it didn't dissolve in RCA-1 solution
after more than 15 minutes, which makes the claim that it's "just a different
etch rate" pretty much bollocks.
Depositing more polysilicon (~300nm) seems like the way to go.
I don't wanna use more, because the higher the poly-thickness, the bigger the
resistance between the Poly-TiSi2 and the actual SiO2 dielectric, which
impairs the frequency behavior of the FETs.
It seems as if the folks have already processed our contract renewal, since I
was able to log in on the NFF website and I'm able to book from Tuesday on
I'll prepare 10 new wafers on Tuesday, where I'll etch the STI and deposit the
first LTO load (4 microns), then CMP 15 minutes, BOE until silicon becomes
visible, again LTO (2 microns), CMP again 10 minutes, which should remove
parts of the Silicon and leave silicon islands surrounded by LTO.
This way I can have a topology which isn't bigger than 200nm in dz (height
difference) which will allow nicely connected polysilicon gates, with h=300nm
And this time I take CKs advice and check every sputter source for the
markings on the back (they scratched the material identifiers on the back he
said) before depositing
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