[Libre-silicon-devel] Silicide formation

Christoph Maier christoph.maier at ieee.org
Mon Mar 11 21:18:52 CET 2019

Hi from Oslo!

So, it turned out that ...

On Thu, Mar 7, 2019 at 3:48 PM Christoph Maier <christoph.maier at ieee.org> wrote:
> Hi from San Diego!
> I'll probably just have arrived in Oslo for a trial lecture (subject:
> How to deal with mismatch in IC design processes)
> and will be too busy travelling to make it to the Mumble ...

I arrived in Oslo just in time to join the Mumble
(and distract my hostess with the Mumble talk, and then, by accident,
y'all with my chat with the hostess)

Now that the trial lecture is done,
I changed its repository status to "public":

Next question:
Y'all, i.e., the people on this list interesed in a freely accessible
silicon IC process,
are also part of the target audience of this lecture,
in the sense that it should set a few things straight what is feasible
in analog IC design and what isn't.

What added information would help clarify for you that analog IC
design comes with specific problems,
that require specific design patterns to overcome them.

Also, David, what would be a good URL to put yet another clickable
hyperlink easter egg to your process description into the PDF,
where I pasted in your process cross-section?

Catching up with a week of sleep deficit,

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