[Libre-silicon-devel] GoFundMe campaign for the clean room

Hagen SANKOWSKI hsank at posteo.de
Wed May 1 17:55:49 CEST 2019


Hello Rudolf!

Comments inside.

On 5/1/19 5:06 PM, Rudolf Usselmann wrote:

> I am very new to this group, so please forgive if I am asking
> something that has been discussed already.

No problem. Thanks for joining our mailing list and a warm welcome :-)

> 1. Do you guys have a standard cell library for this fab ?

Still not, but I am working hard on that. The repository you'll find here

https://github.com/chipforge/StdCellLib

> 2. Whats the smallest features size that can be supported ?

We currently targeting 1 micron, but the equipment we are using is able
to handle 500 nm also.

> 3. Can this chip be mixed analog/digital ?

Yes, definitively, that's what we aimed for.
https://github.com/libresilicon/process

> 4. Do you have any IP for this fab, like a SERDES for example ?

No. Regarding our feature size of 1 micron this is a little bit far ahead.

> 5. Is there any NRE ?

It's up to you. All information you'll need is public. You can hire
someone to do the job for you, or doing it by yourself. In the end, the
Masks have to be done.

> 6. What is the wafer size ?

The Clean Room we are using has equipment for 4 inches, as well as 5 or
6 for some machines. So mainly 4 inches.

> 7. What is the wafer cost ?

Depends on condition / preparation between 10 and 20 bucks for 4 inches.
http://www.nff.ust.hk/en/our-services/charging-scheme.html

> 8. Is there a die size limit ?

Well, regarding the clean room conditions, there is a probability that
with rising die size statistically on every die at least one piece of
dust is causing defects. Your yields goes down to zero.

Better your die size is still small enough to be "between" two pieces of
dust. At 10.000 class clean rooms, practically the limit is somewhere
around 10 by 10 mm.

If the die size is small enough (as our Test Chip less than 5 x 5 mm)
you can safe money by sharing the mask for 4 mask layers.

> 9. What packaging is available to you ?

We not fully evaluate this topic with the lab which will do the
packaging for us - assume all the older, quite saturated packages up to
flip-chip BGA.

> I am trying to grasp what the boundaries of our imagination should> be for proposing a "test chip".

David is currently processing this Test Chip -
https://github.com/chipforge/PearlRiver

We collect there a lot of different circuits, like MOSFETs, Resistors,
Capacities, Diodes, BJT and even Ring Oscillators with some Standard
Cells (NAND3, NOR3 and INV) each with pads around for (mostly) 4-point
measurements.

> I think it can be very easy to get funding for the right chip.

Any suggestions?

Best Regards,
Hagen.

> ===============================================================
> Rudolf Usselmann,    ASICS World Services, LTD,    www.asics.ws
> Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.
> 
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