[Libre-silicon-devel] GoFundMe campaign for the clean room

Rudolf Usselmann rudi at asics.ws
Thu May 2 10:21:33 CEST 2019

On Wed, 2019-05-01 at 17:55 +0200, Hagen SANKOWSKI wrote:
> Hello Rudolf!
> Comments inside.

Thank you for the quick reply Hagen !

> > I think it can be very easy to get funding for the right chip.
> Any suggestions?

Here are a few thoughts ....

Soooo, 1 micron is much larger than I hoped for!

I took a quick look at the standard cell library. Looks like no
flops or latches so far. I wonder if the generated library can
be used with Synopsys DC.

I think you need a few more items before making a commercial chip:

1. Flip Flops (with and without scan support)
2. Latches
3. Gates should have at least 3 different drive strength
4. True 2T SRAM (memory compiler)
5. FLASH memory
6. programmable PLL

It would be interesting to know what the max frequency for a 
32 bit MAC would be (input and output registers only), and what
kind of power consumption to expect.

Almost any chip you make will need to be low power - this is where
everything moves these days.

In my opinion, a 555 will have zero commercial value. You'll have
to make sure the electrical characteristics match whats out there,
or it will not be compatible.

I'm not sure if you guys are just looking for some educational fun
and proof of concept, or really want to make something you can sell.

I think once you have the above listed components, you can seriously
consider making something that can make money.

I would recommend that you try to integrate the above items in your
test chip.

Also, I am still curious to find out more about the cost:

10 cm wafer would get you about 200 x 25 sqmm dies.
Assuming 80% yield you'll end up with about 160 good dies. That's
about $0.125 USD for the dies. 25 sqmm is a very small chip for 1um.

How much will it cost to cut the wafer and package the dies in
some tssop/soic or similar package ?

What are the actual mask costs if you guys do them yourself ?

How about testing the final chips ? Do they have test equipment
that is fully automatic and can test several thousend chips in
a run ? How about binning is that supported ?

What other costs are there ?

And most importantly, if you want to make a commercial chip, what
is the FAB capacity ? If you want to run 10K wafers, or 100k wafers
will they let you ?

Rudolf Usselmann,    ASICS World Services, LTD,    www.asics.ws
Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.

           The agony of poor quality remains long
        after the joy of low cost has been forgotten

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