[Libre-silicon-devel] GoFundMe campaign for the clean room
hsank at posteo.de
Thu May 2 11:47:15 CEST 2019
On 5/2/19 10:21 AM, Rudolf Usselmann wrote:
> On Wed, 2019-05-01 at 17:55 +0200, Hagen SANKOWSKI wrote:
>> Hello Rudolf!
>> Comments inside.
> Thank you for the quick reply Hagen !
Well, decades ago I keep track on opencores.org - and among all the
students project there your code / cores were in the best shape and code
quality. I learned while reading your code. Thank you!
> Here are a few thoughts ....
> Soooo, 1 micron is much larger than I hoped for!
Yes, 1 micron does not sounds very ambitious, but this is the last node
which is more or less completely documented in the textbooks. With
smaller nodes the NDA-foo was disturbing the publication. Some aspects
you'll find in the literature, but not all.
But 1 micron is perfect for analog stuff. All the analog MOSFETs have
huge sizes for driving current.
Our advantage against the original 1 micron node is, that fabs do not
touch the old nodes, do not advanced them with STI or LTO. So we use
techniques which came up later and insert them also into the "old" 1
micron. We guess becoming much better for the node than the original one.
Regarding the "big" feature size, a 1 Micron fits better the needs for
harsh environment, radiation and space exploration. The temperature
range can be extended. Also the supply power hasn't to be such accurate
and stable. 1 Micron better plays with supply voltages between 3 and
let's say 40 Volt e.g. for automotive. Of course, the 5 Volt support for
all the tinkerer and maker in their basement is not a problem.
And once up and running, we can jump further to 0.5 Micron, the
machinery equipment is the same.
> I took a quick look at the standard cell library. Looks like no
> flops or latches so far. I wonder if the generated library can
> be used with Synopsys DC.
The Library is still Work-in-Progress.
Since the library development is a one-man-show, it is not feasible to
draw *all* cells by hand. Last year I started and it took me something
between one and two weeks for only one cell. So estimating a cell count
of 400, I decide to stop hand-crafting all the cells and write a Cell
Generator instead. Unfortunately I am not a programmer, so it also took
me effort to do so. But, yeah, now I see progress in coding the cell
generator, which I called "Popcorn".
> I think you need a few more items before making a commercial chip:
> 1. Flip Flops (with and without scan support)
> 2. Latches
Yes, on the list.
> 3. Gates should have at least 3 different drive strength
Regarding the driving current, the last transistor stage has to become
quite huge, or, you add another buffer with different strength. In this
case, it could also be up to the synthesis tool to buffer up higher
fan-ins or longer lines.
I decide, to draw (smaller) cells with one unified fan-out only and let
the tools do the rest.
> 4. True 2T SRAM (memory compiler)
Yes, on the list.
> 5. FLASH memory
The PearlRiver (Test Wafer) already has some flash cells. They are still
> 6. programmable PLL
PLLs are analog stuff. In lack of the right guy to do so, we first add
Ring Oscillators in to the PearlRiver.
> It would be interesting to know what the max frequency for a
> 32 bit MAC would be (input and output registers only), and what
> kind of power consumption to expect.
> Almost any chip you make will need to be low power - this is where
> everything moves these days.
Yes, our aim to squeeze 1 Micron in this direction.
> In my opinion, a 555 will have zero commercial value. You'll have
> to make sure the electrical characteristics match whats out there,
> or it will not be compatible.
> I'm not sure if you guys are just looking for some educational fun
> and proof of concept, or really want to make something you can sell.
> I think once you have the above listed components, you can seriously
> consider making something that can make money.
> I would recommend that you try to integrate the above items in your
> test chip.
You can look, what is already on the PearlRiver. Currently in Magic, the
documentation is unfortunately still not complete.
> Also, I am still curious to find out more about the cost:
> 10 cm wafer would get you about 200 x 25 sqmm dies.
> Assuming 80% yield you'll end up with about 160 good dies. That's
> about $0.125 USD for the dies. 25 sqmm is a very small chip for 1um.
> How much will it cost to cut the wafer and package the dies in
> some tssop/soic or similar package ?
> What are the actual mask costs if you guys do them yourself ?
One Mask was around 125 $ if I remember right. Depending on the
technology features you like to use there are up to 18 (?) masks. This
details David better know than me.
> How about testing the final chips ? Do they have test equipment
> that is fully automatic and can test several thousend chips in
> a run ? How about binning is that supported ?
No. This is still a topic we have to solve. The lab has 4-point-Tester,
but need manual effort to adjust the probes. Fully automatic stuff costs
always the adapter plate for some thousands bucks.
> What other costs are there ?
Well, we developing the technology in a University Lab and maintain some
contacts to a regular Fab which is willing to adapt our process on their
machines. Assuming we are successfully and can adapt the process to more
fabs, the price becomes competitive.
> And most importantly, if you want to make a commercial chip, what
> is the FAB capacity ? If you want to run 10K wafers, or 100k wafers
> will they let you ?
Once we got from the mentioned fab above an offer for 25k Waver per
Month, regarding a normal yield this are 4M up to 20M Dies per Month.
Hard to sale, isn't it?
> Rudolf Usselmann, ASICS World Services, LTD, www.asics.ws
> Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.
> The agony of poor quality remains long
> after the joy of low cost has been forgotten
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