[Libre-silicon-devel] "555" Repository + Schematic
david.lanzendoerfer at o2s.ch
Fri May 3 07:02:20 CEST 2019
Our gate oxide is 40nm thick which means that the break through happens at
around 40V DC from gate to bulk.
Then of course there is the issue with the depletion zone and latch up
I've increased the trench depth to 3.5 microns and we have virtually no Ld and
a very shallow doping which means that Cj (junction capacity) is really low
and the channel length is basically equal to the gate with (1 micron).
In general that means, that the isolation properties from Drain to Source (and
Bulk for what it's worth) are even better than 40V probably.
We'll see on Monday, hopefully.
Anyway... The target for the absolute maximum ratings are 40V.
I've taken standard models from other manufacturers and have put the
parameters for which I've dimensioned our geometry.
And at least SPICE told me, the magic smoke won't come out.
Now that we have spacers, I can finally check on Monday, whether I've done my
On Friday, 3 May 2019 12:47:38 PM HKT ludwig jaffe wrote:
> Hi all scale it up.
> I would make it bigger, lets say 4 micron as the circuit is more reliable
> with bigger transistors, so it survives misuse to a higher degree and as
> the 555 is not so complicated one could use more chip area. It would be
> good to be at least compatible with 4000 cmos logic which works upto 20v.
> If the 555 survives 30v it wkuld be an interesting feature. Also have big
> output transistors so one can directly drive a big mosfet with a big gate
> capacity. So one can do pwm with a mosfet and our 555 to control dc motors
> or to build simple switchmode power supplies.
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