[Libre-silicon-devel] Analog design toolchain for 555
hsank at posteo.de
Tue May 21 20:45:07 CEST 2019
On 5/20/19 1:48 AM, Éger Ferenc wrote:
> The tools so far (RFC if you think there's a better option):
> gschem 1.8.2 (schematic capture)
lepton-schematic --version > 1.9.7 (git: f3a8714)
> gnetlist 1.8.2 (netlist extractor, alleged source is at
lepton-netlist > 220.127.116.1181211 (git: f3a8714)
> gspiceui 1.1.00 or 1.2.36 (orchestrates netlist extraction, deck
> generation, simulator invocation, waveform viewer invocation, like ADE,
> source: https://sourceforge.net/projects/gspiceui/)
> ngspice 26 (simulator)
ngspice > 30
> gaw (waveform viewer)
Well, I use lepton-EDA here, installed under Debian SID (somehow a
The killer-feature IMHO is the possibility to compare two schematic
versions graphical by
git difftool -x lepton-schdiff Sources/geda/555_Book-Version.sch
> Problems discovered so far:
> 1. In gschem, components automatically get '?' refdes on place or copy.
> Refdes must be unique, therefore it is beneficial to insert some lines
Just after drawing the schematic follows a numbering-step with
lepton-refdes_renum or lepton-renum = two tools for the same step.
> 2. gnetlist makes use of the gschemrc configuration to establish mapping
> between symbols and sub-schematics (subsch is not recorded in the
> schematic, but in the symbol file). However, gspiceui invokes gnetlist
> not in the current working directory, but where the schematic is loaded
> from, so local gschemrc is not parsed. Possible solutions:
> - Adapt a flat directory structure (no sources, tbench, ...). Ugly but
> - Place a link to the local gschemrc everywhere
> - Set libraries in the global gschemrc (not good because necessary
> config no longer contained in the project dir)
> - Patch gspiceui (PrcGNetList.cpp 396)
> - Invoke gnetlist manually outside gspiceui and import complete netlist
I still figuring out the best solution.
> 3. In case of hierarchical designs flattened into a single circuit,
> gnetlist places '/' into net names and component names ("X1/R1 11 7
> 100k"). This breaks ngspice (interpreted like "X1 R1 11 7 100k"). Blind
> replacement does not help, as if we use parametric models, we may need
> expressions containing division.
The link you mentioned regarding the hierarchical designs contains the
hint, that with configuration we are able to append the component name
tag after the Circuit, eg. R1_X1 which would work for us.
The gnetlistrc with this configuration I'll add soon to the git repository.
> 4. Nets in lower levels and nets at higher levels connected to them are
> treated as separate entities and not connected, for example:
> MX1/M26 X1/OUTPUT 18 X1/GND X1/GND nmos4 l=0.5u w=20u
> R3 1 5 100 (shall be R3 1 X1/OUTPUT 100)
> Maybe the wrong port symbol is used in the lower level, this needs to be
> checked first.
See answer for 3.
> 5. When flattening hierarchical designs, component designators sometimes
> have wrong first letter (first letter denotes component type).
> Particularly, MOS works but resistors are not:
See answer for 3.
> Maybe a solution is to use either a .SUBCKT instead of flattening (good
> only if internal nodes remain query-able), or to use a single schematic
> page (ugly).
Yes. I prefer the .SUBCKT solution with Toplevel just containing the
test bench and the circuit is hidden (and inter-changeable).
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