[Libre-silicon-devel] Design rules...
david.lanzendoerfer at lanceville.cn
Thu May 30 09:11:52 CEST 2019
We need some design rules, otherwise this will never work.
Those rules aren't just there for fun, or to make the life of the layout
designer more difficult, they actually have a purpose.
I've got to introduce two important design rules now, which are needed,
because otherwise it's virtually impossible for me to guarantee working
1) n-well/p-well have to be at least 5 microns apart from each other.
Reason: The isolation trench between the wells is around 2.5~3.5 microns deep
(variation due to CMP variation)
Wet etching has a 45 degree angle and dry etching isn't a perfect 90 degree
angle either, so in order to make sure, that the individual pull-up/pull-down
paths or whatever are properly isolated to each other, the wells have to have
a spacing of at least 5-7 microns (do the geometry/math)
2) holes within the contact,via1,via2,via3 layer all have to have the *exact*
same size and dimensions. I had good results with the 2um x 2um holes.
Reason: Depending on the area, the etching rate of HF acid as well as the dry
etcher is varying.
While in the smaller contact holes, there was still residue of LTO visible
under the microscope, in the big holes nearly all of the silicide was already
In the future I will add export filter back into cifoutput, which turns all
contact holes, which are bigger than 2u x 2u into an array of 2u x 2u holes,
and anything smaller will give you a DRC error.
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