[Libre-silicon-devel] PAD Cells
hsank at posteo.de
Sun Nov 3 10:01:21 CET 2019
While doing some homework regarding our PAD cells, I once again looked
into the MOSIC Design Rules for Scalable CMOS .
Out of Rule Set 10.x we get the mimimum grid for bonding pad areas with
So my question is here, do somebody has access to bonding machines and
their documentation and can provide the grid of bonding pad areas this
machines usually can handle?
Is this 95u/100u as I still remember? Or are this machines already in
the milli-inch-measured domain, e.g. 4 mil for 101.6u?
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