[Libre-silicon-devel] PAD Cells

David Lanzendörfer leviathan at libresilicon.com
Sun Nov 3 13:46:00 CET 2019

At HKUST there is a packaging lab which can also do flip chip bonding,
as well as blob chip bonding.


On Sunday, 3 November 2019 8:33:59 PM HKT Staf Verhaegen wrote:
> Goodday Hagen,
> I think the question is better phrased as to which packaging equipment
> LibreSilicon has access to and how much money they want to pay. I think
> advanced wire-bonding can go to pad openings of 50um by 50um or below. The
> most recent trend is I think to go for flip-chip bonding and not
> wire-bonding though for advanced chips with high speed signals.
> In the IO libraries we developed at my previous work place we did not
> integrate the bonding pads in the IO cells and we provided different sets
> of bonding pads and custom ones could even be generated for the customer.
> For space application typically wedge wire-bonding needs to be used and
> this needs bigger pad openings; some application can live with ball wire
> bonding and use smaller pad openings. greets,
> Staf.
> Hagen SANKOWSKI schreef op zo 03-11-2019 om 10:01 [+0100]:
> > Hello List!
> > While doing some homework regarding our PAD cells, I once again lookedinto
> > the MOSIC Design Rules for Scalable CMOS [0]. Out of Rule Set 10.x we get
> > the mimimum grid for bonding pad areas with102 micron. So my question is
> > here, do somebody has access to bonding machines andtheir documentation
> > and can provide the grid of bonding pad areas thismachines usually can
> > handle? Is this 95u/100u as I still remember? Or are this machines
> > already inthe milli-inch-measured domain, e.g. 4 mil for 101.6u?
> > Curious,Hagen.
> > [0] https://www.mosis.com/files/scmos/scmos.pdf

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