[Libre-silicon-devel] [libre-riscv-dev] [OT only slightly] STEAM Camp OpenSourceEcology 22jan2020 for 9 days

whygee at f-cpu.org whygee at f-cpu.org
Wed Jan 1 00:53:18 CET 2020

Happy new year everybody !

On 2020-01-01 00:28, Luke Kenneth Casson Leighton wrote:
> On 12/31/19, Marcin Jakubowski <marcin at opensourceecology.org> wrote:
>> Luke, any thoughts on you stepping up and coordinating the maskless 
>> stepper
>> module of this crazy evolution?
> as we (privately) discussed yesterday, there are 4 levels of NDAs: HDL
> tools, VLSI tools, Cell Libraries and Foudries.
> i'm waaay overloaded by dealing with level 1 heavily and interacting
> with people at level 2 and 3.
> david and the libre-silicon team are dealing with level *4* heavily,
> level 3 in a big way, and interacting with people at levels 2 and 1.
> they're the best people for this.

So who should I ask for help with 3 and 4 ?

My microcontroller design is progressing well,
I'm getting down to individual cells and I bootstrapped
the design with ProASIC3 FPGA cells but without
precharacterised cell libraries and other silicon-proven
information, I can not estimate the timings.
Not to mention that things like SRAM arrays are a whole
new territory...

Thanks for letting me discover about libresilicon !

> l.

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