From pg at futureware.at Sat May 9 21:27:22 2020 From: pg at futureware.at (Philipp =?iso-8859-1?Q?G=FChring?=) Date: Sat, 09 May 2020 21:27:22 +0200 Subject: [Libre-silicon-devel] PearlRiver NG Message-ID: Hi, Could we create larger PearlRiver like Testwafers, or is it already the largest size possible on our wafers? I would like to add some more structures on PearlRiver. Can I just enlarge it, or do I have to replace things? What would be the maximum size? According to David: "ideally we wanna make the next PearlRiver even smaller, rather than bigger, because the more dies you can fit on one wafer the better you can characterize issues with edge effects" What we could do is splitting the test structures across multiple test wafers based on the complexity level a lab can do. If a lab can't build polysilicon for instance, it's pointless for them to test polysilicon zener diodes." My idea at the moment is to build a Test Wafer generator which would help us there. Lets try to discuss this tomorrow in the Mumble call. Best regards, Philipp From eegerferenc at gmail.com Sun May 10 16:56:42 2020 From: eegerferenc at gmail.com (=?UTF-8?B?w4lnZXIgRmVyZW5j?=) Date: Sun, 10 May 2020 16:56:42 +0200 Subject: [Libre-silicon-devel] PearlRiver NG In-Reply-To: References: Message-ID: Hello Everyone, We agreed on today's mumble session that we will follow a "modular" approach on PRNG: instead of layouting and distributing a complete chip in GDS2, there shall be certain modules from which the implementer can assemble their own test chip, customized to the technology capabilities of the fab. For example, you need Rsq for base wells and collector wells if you actually implant them, and this is also valid for HVMOS, ISOMOS and BJT devices. Similarly, You don't need to waste space for Z-diodes if you have no RTP or poly altogether. Rationale: - PR1 is already 4x4mm2, which may not fit on all steppers of the world. With the modular approach, the implementer can take the aspect ratio and size limitations of its stepper into account. - By eliminating modules that are not needed, space can be freed up to insert new or custom test structures. - It is also possible and desirable to make the chip smaller, so edge effects on the wafer can be estimated more accurately (and more chips to measure also reduces uncertainity in statistical process control). - The modules can also be re-used to design PCM stripes or dies for live manufacturing as well... One important thing is that the modules must have an outer dummy ring on the relevant layers, as we will no longer have control on what is placed near what. The dummy rings are aimed to ensure consistent microenvironment during processing, so layout-dependent effects will not influence the performance of individual modules, keeping results from different implementations comparable. Regards, Ferenc On Sat, May 9, 2020 at 9:27 PM Philipp G?hring wrote: > Hi, > > Could we create larger PearlRiver like Testwafers, > or is it already the largest size possible on our > wafers? > > I would like to add some more structures on > PearlRiver. Can I just enlarge it, or do I have to > replace things? > What would be the maximum size? > > According to David: > "ideally we wanna make the next PearlRiver even > smaller, rather than bigger, because the more dies > you can fit on one wafer the better you can > characterize issues with edge effects" > What we could do is splitting the test structures > across multiple test wafers based on the complexity > level a lab can do. If a lab can't build > polysilicon for instance, it's pointless for them > to test polysilicon zener diodes." > > My idea at the moment is to build a Test Wafer > generator which would help us there. > > Lets try to discuss this tomorrow in the Mumble > call. > > Best regards, > Philipp > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers > -------------- next part -------------- An HTML attachment was scrubbed... URL: From eegerferenc at gmail.com Mon May 18 22:06:00 2020 From: eegerferenc at gmail.com (=?UTF-8?B?w4lnZXIgRmVyZW5j?=) Date: Mon, 18 May 2020 22:06:00 +0200 Subject: [Libre-silicon-devel] Badgood news on USA/TSMC/Huawei Message-ID: Hello Everyone, Today I ran about two interesting articles (they are unfortunately in Hungarian, but they may be found in English somewhere, or use a translator): https://index.hu/gazdasag/2020/05/15/a_feher_haz_fokozza_a_nyomast_a_huaweire/ https://index.hu/techtud/2020/05/18/huawei_egyesult_allamok_amerika_kereskedelmi_korlatozasok_csipgyartas_tsmc_kirin/ Short warp-up: 1. USA government practically bans domestic and overseas licensees and users of US semiconductor IP and technology (including fab equipment) worldwide to do business with the Chinese, 2. Huawei's supplier TSMC stops accepting orders from Huawei, 3. TSMC opens new fab and relocates R+D to the USA for USD12bn. The bad side is that (besides the apparent restart of the Cold War) our experience with HKUST's CMP machine (no spare parts) may become the new global norm in the near future. The good side is that the bad side may undermine trust in the reliablity of US suppliers and devaluate their IP, while up-rating the value and importance of the open-source, worldwidely distributed silicon ecosystem that is not bound to to any corporation bound to a government (e.g. Kyrin is more or less based on ARM, whose licensing and subjection to US export control is an attack surface, while its direct competitor RISC-V is free of such restrictions), as companies may perceive either the US may say "You are the next who is locked out", or their non-US supplier may say next " I lock You out". Regards, Ferenc -------------- next part -------------- An HTML attachment was scrubbed... URL: From lkcl at lkcl.net Mon May 18 22:52:25 2020 From: lkcl at lkcl.net (Luke Kenneth Casson Leighton) Date: Mon, 18 May 2020 21:52:25 +0100 Subject: [Libre-silicon-devel] Badgood news on USA/TSMC/Huawei In-Reply-To: References: Message-ID: https://slashdot.org/story/20/05/18/188211/china-injects-22-billion-into-local-chip-firm From pavel at noa-labs.com Tue May 19 00:47:21 2020 From: pavel at noa-labs.com (Pavel Nikulin) Date: Tue, 19 May 2020 04:47:21 +0600 Subject: [Libre-silicon-devel] Badgood news on USA/TSMC/Huawei In-Reply-To: References: Message-ID: That was the writing on the wall. Not only the bleeding edge availability now put to doubt, even seemingly routine 90nm+ tapeouts on mature nodes are only hanging by 3-4 fabs if you need volume. The industry needs a 300mm wafer solution for high volume 90-180nm parts, but as everybody went chasing the bleeding edge, not much capacity is remaining on "legacy" nodes. 200mm doesn't cut it for popular ICs that don't benefit a lot economically from advanced nodes. So now, they not only left without latest nodes, but have to go to Taiwan even for making something like the simplest MCUs, discrete logic, and 74 series parts. No need to mention that the situation with specialty fabs would be even worse. On Tue, May 19, 2020 at 2:06 AM ?ger Ferenc wrote: > > Hello Everyone, > > Today I ran about two interesting articles (they are unfortunately in Hungarian, but they may be found in English somewhere, or use a translator): > > https://index.hu/gazdasag/2020/05/15/a_feher_haz_fokozza_a_nyomast_a_huaweire/ > https://index.hu/techtud/2020/05/18/huawei_egyesult_allamok_amerika_kereskedelmi_korlatozasok_csipgyartas_tsmc_kirin/ > > Short warp-up: > 1. USA government practically bans domestic and overseas licensees and users of US semiconductor IP and technology (including fab equipment) worldwide to do business with the Chinese, > 2. Huawei's supplier TSMC stops accepting orders from Huawei, > 3. TSMC opens new fab and relocates R+D to the USA for USD12bn. > > The bad side is that (besides the apparent restart of the Cold War) our experience with HKUST's CMP machine (no spare parts) may become the new global norm in the near future. > > The good side is that the bad side may undermine trust in the reliablity of US suppliers and devaluate their IP, while up-rating the value and importance of the open-source, worldwidely distributed silicon ecosystem that is not bound to to any corporation bound to a government (e.g. Kyrin is more or less based on ARM, whose licensing and subjection to US export control is an attack surface, while its direct competitor RISC-V is free of such restrictions), as companies may perceive either the US may say "You are the next who is locked out", or their non-US supplier may say next " I lock You out". > > Regards, > Ferenc > > > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers