From hsank at posteo.de Sat Jul 3 09:53:12 2021 From: hsank at posteo.de (Hagen SANKOWSKI) Date: Sat, 3 Jul 2021 07:53:12 +0000 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-04 @ 18:00 UTC Message-ID: <440ecd54-35dd-f928-3202-5777911376e0@posteo.de> Hello List! This is our weekly announcement for the next Mumble Sessions on Sunday 2021-07-04 @ 18:00 UTC. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. We like to follow-up our topics from mumble sessions before. Regards, Hagen. From leviathan at libresilicon.com Mon Jul 5 17:15:01 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Mon, 05 Jul 2021 16:15:01 +0100 Subject: [Libre-silicon-devel] Affordable RISC-V chips Message-ID: <5020464.ADf4hGXZ5F@harvey> Hi list I came across this article here and I'm going to buy some chips to develop some hardware prototypes. I was thinking about testing energy and speed on a devboard and then think about consumer products I could build with it, like a laptop or a tablet. I was wondering whether someone of you wants to join as well. https://www.cnx-software.com/2021/07/05/xiangshan-open-source-64-bit-risc-v-processor-rival-arm-cortex-a76/ Cheers -lev -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From hsank at posteo.de Sat Jul 10 17:19:03 2021 From: hsank at posteo.de (Hagen SANKOWSKI) Date: Sat, 10 Jul 2021 15:19:03 +0000 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-11 @ 18:00 UTC Message-ID: <03322ff8-c1a4-2b71-f8dd-c70f7a069c79@posteo.de> Hello List! This is our weekly announcement for the next Mumble Sessions on Sunday 2021-07-11 @ 18:00 UTC. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. We like to follow-up our topics from mumble sessions before. Regards, Hagen. From leviathan at libresilicon.com Sun Jul 11 21:07:56 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Sun, 11 Jul 2021 20:07:56 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-11 @ 18:00 UTC In-Reply-To: <03322ff8-c1a4-2b71-f8dd-c70f7a069c79@posteo.de> References: <03322ff8-c1a4-2b71-f8dd-c70f7a069c79@posteo.de> Message-ID: <19133028.DT1ndP76xO@harvey> Hello List So after today's meeting we decided that we'll start writing the specs for a RISC-V platform, based on Chisel, where we strip away everything analog, so that we can synthesize and build it with Phillip's Sky130 standard cells, which he has generated. Graphics will be DVI-D The RAM bus will be implemented using HyperRAM USB can also be implemented without nasty analog hard IP cores. The first iteration will only support a framebuffer, until Luke gets his open source GPU working. I've created a Redmine project for it: https://redmine.libresilicon.com/projects/pure-digital Cheers -lev On Saturday, July 10, 2021 4:19:03 PM WEST Hagen SANKOWSKI wrote: > Hello List! > > This is our weekly announcement for the next Mumble Sessions on Sunday > > 2021-07-11 @ 18:00 UTC. > > Please join us as usual at our Mumble Server murmur.libresilicon.com at > Port 64738, the Channel is IC. > > We like to follow-up our topics from mumble sessions before. > > Regards, > Hagen. > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From christoph.maier at ieee.org Thu Jul 15 21:52:45 2021 From: christoph.maier at ieee.org (Christoph Maier) Date: Thu, 15 Jul 2021 21:52:45 +0200 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-11 @ 18:00 UTC In-Reply-To: <19133028.DT1ndP76xO@harvey> References: <03322ff8-c1a4-2b71-f8dd-c70f7a069c79@posteo.de> <19133028.DT1ndP76xO@harvey> Message-ID: Meanwhile, I'm slacking in Virtual Telluride and finally getting around learning the analog design flow for skywater. Hopefully, this will eventually converge. And Now For Something Completely Different: David, did twitter cancel you? Can't seem to send messages to leviathanch any more. Brumm! Christoph On Sun, Jul 11, 2021 at 9:08 PM David Lanzend?rfer wrote: > > Hello List > So after today's meeting we decided that we'll start writing the specs for a > RISC-V platform, based on Chisel, where we strip away everything analog, > so that we can synthesize and build it with Phillip's Sky130 standard cells, > which he has generated. > Graphics will be DVI-D > The RAM bus will be implemented using HyperRAM > USB can also be implemented without nasty analog hard IP cores. > The first iteration will only support a framebuffer, until Luke gets > his open source GPU working. > I've created a Redmine project for it: > https://redmine.libresilicon.com/projects/pure-digital > > Cheers > -lev > > On Saturday, July 10, 2021 4:19:03 PM WEST Hagen SANKOWSKI wrote: > > Hello List! > > > > This is our weekly announcement for the next Mumble Sessions on Sunday > > > > 2021-07-11 @ 18:00 UTC. > > > > Please join us as usual at our Mumble Server murmur.libresilicon.com at > > Port 64738, the Channel is IC. > > > > We like to follow-up our topics from mumble sessions before. > > > > Regards, > > Hagen. > > _______________________________________________ > > Libresilicon-developers mailing list > > Libresilicon-developers at list.libresilicon.com > > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers > > > -- > (\__/) > (='.'=) This is Ninja Bunny. > (")_(") > Copy and paste Bunny into your > signature to help him gain world domination > > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers From leviathan at libresilicon.com Fri Jul 16 00:26:27 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Thu, 15 Jul 2021 23:26:27 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-11 @ 18:00 UTC In-Reply-To: References: <03322ff8-c1a4-2b71-f8dd-c70f7a069c79@posteo.de> <19133028.DT1ndP76xO@harvey> Message-ID: <3101452.ymqWu7nX4s@harvey> Hi I decided to delete my Twitter account because it's a cesspool of toxicity. It was the best decision I made, since I've decided to get rid of my TV decades ago. Cheers -lev On Thursday, July 15, 2021 8:52:45 PM WEST Christoph Maier wrote: > Meanwhile, I'm slacking in Virtual Telluride and finally getting > around learning the analog design flow for skywater. > Hopefully, this will eventually converge. > > And Now For Something Completely Different: > David, did twitter cancel you? Can't seem to send messages to > leviathanch any more. > > Brumm! > Christoph > > On Sun, Jul 11, 2021 at 9:08 PM David Lanzend?rfer > > wrote: > > Hello List > > So after today's meeting we decided that we'll start writing the specs for > > a RISC-V platform, based on Chisel, where we strip away everything > > analog, so that we can synthesize and build it with Phillip's Sky130 > > standard cells, which he has generated. > > Graphics will be DVI-D > > The RAM bus will be implemented using HyperRAM > > USB can also be implemented without nasty analog hard IP cores. > > The first iteration will only support a framebuffer, until Luke gets > > his open source GPU working. > > I've created a Redmine project for it: > > https://redmine.libresilicon.com/projects/pure-digital > > > > Cheers > > -lev > > > > On Saturday, July 10, 2021 4:19:03 PM WEST Hagen SANKOWSKI wrote: > > > Hello List! > > > > > > This is our weekly announcement for the next Mumble Sessions on Sunday > > > > > > 2021-07-11 @ 18:00 UTC. > > > > > > Please join us as usual at our Mumble Server murmur.libresilicon.com at > > > Port 64738, the Channel is IC. > > > > > > We like to follow-up our topics from mumble sessions before. > > > > > > Regards, > > > Hagen. > > > _______________________________________________ > > > Libresilicon-developers mailing list > > > Libresilicon-developers at list.libresilicon.com > > > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers > > > > -- > > (\__/) > > (='.'=) This is Ninja Bunny. > > (")_(") > > Copy and paste Bunny into your > > signature to help him gain world domination > > > > _______________________________________________ > > Libresilicon-developers mailing list > > Libresilicon-developers at list.libresilicon.com > > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From hsank at posteo.de Sat Jul 17 12:49:14 2021 From: hsank at posteo.de (Hagen SANKOWSKI) Date: Sat, 17 Jul 2021 10:49:14 +0000 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC Message-ID: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Hello List! This is our weekly announcement for the next Mumble Sessions on Sunday 2021-07-18 @ 18:00 UTC. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. We like to follow-up our topics from mumble sessions before. Regards, Hagen. From christoph.maier at ieee.org Sat Jul 17 17:35:00 2021 From: christoph.maier at ieee.org (Christoph Maier) Date: Sat, 17 Jul 2021 17:35:00 +0200 Subject: [Libre-silicon-devel] Fwd: Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: Oops, forgot to forward to the group. In all fairness to the neuromorphs, they kept one more slide in the deck, but they moved it all the way to the end and didn't present it. https://docs.google.com/presentation/d/1El7U_EbFTuB5D5w-drW5fdWDpSrf05OthE9Ng49OFK8/edit#slide=id.ge4ea253363_0_12 tatzelbrumm ---------- Forwarded message --------- From: Christoph Maier Date: Sat, Jul 17, 2021 at 5:20 PM Subject: Re: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC To: Hagen SANKOWSKI Now that the Telluride Neuromorphic Workshop is over, where I just played with my M?rklin train on the public record: https://youtu.be/3X-5Q-h6qjY?t=6502 I need to pay attention to what you're doing again ... in particular how far you are with getting skywater-pdk to work. What I did for the Telluride crowd wasn't considered very presentable. Of the stuff I did: https://github.com/MastellaM/sky130_TAC3/pull/3 only one slide made it into The Final Presentation: https://youtu.be/3X-5Q-h6qjY?t=2207 , and it was considered somewhat out of place. tatzelbrumm On Sat, Jul 17, 2021 at 12:49 PM Hagen SANKOWSKI wrote: > > Hello List! > > This is our weekly announcement for the next Mumble Sessions on Sunday > > 2021-07-18 @ 18:00 UTC. > > Please join us as usual at our Mumble Server murmur.libresilicon.com at > Port 64738, the Channel is IC. > > We like to follow-up our topics from mumble sessions before. > > Regards, > Hagen. > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers From leviathan at libresilicon.com Sun Jul 18 21:39:53 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Sun, 18 Jul 2021 20:39:53 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: <2198090.IbNUyZpdlT@harvey> Hi So today we've been talking about ways around having to use DDR3/DDR4 interfaces for external memory of a potential SoC but as it turns outs, all our candidates like HyperRAM or MRAM are out of the window because of the prices. As usual I came back to the question "is it possible to do this with an AVR?" which usually helps me at fixing such problems and I came across those projects here: https://www.circuitlake.com/interfacing-dram-memory-with-avr.html https://github.com/jnk0le/AVR-DRAM Turns out that it's possible to speak to DRAM over a DDR3 without a special controller, just over GPIO. They got an Atmega to access a Hitatchi M5M44800. The RAM access will be slow, but we don't need to know about the analog properties of the process in order to achieve this. I will probably implement this for my test SoC on a CPLD. Hagen will explain more in the follow up/minutes. Cheers -lev On Saturday, July 17, 2021 11:49:14 AM WEST Hagen SANKOWSKI wrote: > Hello List! > > This is our weekly announcement for the next Mumble Sessions on Sunday > > 2021-07-18 @ 18:00 UTC. > > Please join us as usual at our Mumble Server murmur.libresilicon.com at > Port 64738, the Channel is IC. > > We like to follow-up our topics from mumble sessions before. > > Regards, > Hagen. > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From hsank at posteo.de Sun Jul 18 21:51:41 2021 From: hsank at posteo.de (Hagen SANKOWSKI) Date: Sun, 18 Jul 2021 19:51:41 +0000 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: Meeting Minutes of the Mumble session today =========================================== Participants: Devon, tatzelbrumm (partly), hsank, leviathan Topics ------ - (external) RAM While thinking about an RISC-V CPU demonstrator, we need memory for loading an Operating System like Linux. Our first guess was for the demonstrator just to use external RAM chips, e.g. with HyperRAM, which has a quite simple interface and can be driven without LVDS-IO-Pads (which are still not available for us). Unfortunately using a couple of them gets fast quite expansive. Using commercial available (and cheaper) DRAM nowadays is out of reach for us - this chips using a proprietary interface called DDR2 or DDR3. This interface needs differential IO-Pads (the LVDS we already mentioned above) and is critical about timing (in the meaning of different wire length, wire resistance and so on). Without a PDK for a technology we can not design the analog stuff inside 'cause we still miss all the concrete values for the layers to calculate transistor and wire sizes. - alternative: internal hand-crafted RAM-cells Designing internal RAM cells, no matter whether dynamic RAM or static RAM isn't possible without the analog values from the PDK.. - possible pathes to go * Reducing the Operating System to smaller memory footprints (e.g. with NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU * Getting a PDK and design with a couple of iterations in silicon our analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works.. '''' Note: if we'd start with an alien PDK we had to re-design the analog stuff from ground up again for our LibreSilicon PDK again.. '''' If you have some suggestions how to get out of our chicken-and-egg-Problem, please drop us an email :-) Regards, Hagen From leviathan at libresilicon.com Mon Jul 19 02:47:31 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Mon, 19 Jul 2021 01:47:31 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: <18279928.81D8rRtk9X@harvey> Hi I've been thinking about this Atmega project which communicated with a DDR3 chip using GPIOs. I think I'm going to try this out with an FPGA. The data transfer rate will probably be terrible, but it seems to be an option. Opinions? Cheers -lev On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote: > Meeting Minutes of the Mumble session today > =========================================== > > Participants: Devon, tatzelbrumm (partly), hsank, leviathan > > > Topics > ------ > > - (external) RAM > > While thinking about an RISC-V CPU demonstrator, we need memory for > loading an Operating System like Linux. > > Our first guess was for the demonstrator just to use external RAM chips, > e.g. with HyperRAM, which has a quite simple interface and can be driven > without LVDS-IO-Pads (which are still not available for us). > Unfortunately using a couple of them gets fast quite expansive. > > Using commercial available (and cheaper) DRAM nowadays is out of reach > for us - this chips using a proprietary interface called DDR2 or DDR3. > This interface needs differential IO-Pads (the LVDS we already mentioned > above) and is critical about timing (in the meaning of different wire > length, wire resistance and so on). > > Without a PDK for a technology we can not design the analog stuff inside > 'cause we still miss all the concrete values for the layers to calculate > transistor and wire sizes. > > - alternative: internal hand-crafted RAM-cells > > Designing internal RAM cells, no matter whether dynamic RAM or static > RAM isn't possible without the analog values from the PDK.. > > - possible pathes to go > > * Reducing the Operating System to smaller memory footprints (e.g. with > NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU > > * Getting a PDK and design with a couple of iterations in silicon our > analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works.. > > '''' > Note: if we'd start with an alien PDK we had to re-design the analog > stuff from ground up again for our LibreSilicon PDK again.. > '''' > > If you have some suggestions how to get out of our > chicken-and-egg-Problem, please drop us an email :-) > > > Regards, > Hagen > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From leviathan at libresilicon.com Mon Jul 19 04:13:14 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Mon, 19 Jul 2021 03:13:14 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: <3315853.DKZf9TChYK@harvey> Hi I just came across this IP core, which apparently can talk to normal DDR3 RAM without a special type of pads or controller... https://opencores.org/projects/ddr3_sdram I think I'll gonna try it :-) Cheers -lev On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote: > Meeting Minutes of the Mumble session today > =========================================== > > Participants: Devon, tatzelbrumm (partly), hsank, leviathan > > > Topics > ------ > > - (external) RAM > > While thinking about an RISC-V CPU demonstrator, we need memory for > loading an Operating System like Linux. > > Our first guess was for the demonstrator just to use external RAM chips, > e.g. with HyperRAM, which has a quite simple interface and can be driven > without LVDS-IO-Pads (which are still not available for us). > Unfortunately using a couple of them gets fast quite expansive. > > Using commercial available (and cheaper) DRAM nowadays is out of reach > for us - this chips using a proprietary interface called DDR2 or DDR3. > This interface needs differential IO-Pads (the LVDS we already mentioned > above) and is critical about timing (in the meaning of different wire > length, wire resistance and so on). > > Without a PDK for a technology we can not design the analog stuff inside > 'cause we still miss all the concrete values for the layers to calculate > transistor and wire sizes. > > - alternative: internal hand-crafted RAM-cells > > Designing internal RAM cells, no matter whether dynamic RAM or static > RAM isn't possible without the analog values from the PDK.. > > - possible pathes to go > > * Reducing the Operating System to smaller memory footprints (e.g. with > NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU > > * Getting a PDK and design with a couple of iterations in silicon our > analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works.. > > '''' > Note: if we'd start with an alien PDK we had to re-design the analog > stuff from ground up again for our LibreSilicon PDK again.. > '''' > > If you have some suggestions how to get out of our > chicken-and-egg-Problem, please drop us an email :-) > > > Regards, > Hagen > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From leviathan at libresilicon.com Mon Jul 19 16:06:15 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Mon, 19 Jul 2021 15:06:15 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: <1708039.aBdhkbDZGf@harvey> DRAM DDR3 without leveling IS an option. We don't need special pads and can just use the I/O pads :-) https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/an/ an520.pdf There we go! =^_^=~~~~~ On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote: > Meeting Minutes of the Mumble session today > =========================================== > > Participants: Devon, tatzelbrumm (partly), hsank, leviathan > > > Topics > ------ > > - (external) RAM > > While thinking about an RISC-V CPU demonstrator, we need memory for > loading an Operating System like Linux. > > Our first guess was for the demonstrator just to use external RAM chips, > e.g. with HyperRAM, which has a quite simple interface and can be driven > without LVDS-IO-Pads (which are still not available for us). > Unfortunately using a couple of them gets fast quite expansive. > > Using commercial available (and cheaper) DRAM nowadays is out of reach > for us - this chips using a proprietary interface called DDR2 or DDR3. > This interface needs differential IO-Pads (the LVDS we already mentioned > above) and is critical about timing (in the meaning of different wire > length, wire resistance and so on). > > Without a PDK for a technology we can not design the analog stuff inside > 'cause we still miss all the concrete values for the layers to calculate > transistor and wire sizes. > > - alternative: internal hand-crafted RAM-cells > > Designing internal RAM cells, no matter whether dynamic RAM or static > RAM isn't possible without the analog values from the PDK.. > > - possible pathes to go > > * Reducing the Operating System to smaller memory footprints (e.g. with > NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU > > * Getting a PDK and design with a couple of iterations in silicon our > analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works.. > > '''' > Note: if we'd start with an alien PDK we had to re-design the analog > stuff from ground up again for our LibreSilicon PDK again.. > '''' > > If you have some suggestions how to get out of our > chicken-and-egg-Problem, please drop us an email :-) > > > Regards, > Hagen > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From leviathan at libresilicon.com Tue Jul 20 17:35:19 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Tue, 20 Jul 2021 16:35:19 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: <78508e39a62f040e6b06883a91510754@posteo.de> References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> <1708039.aBdhkbDZGf@harvey> <78508e39a62f040e6b06883a91510754@posteo.de> Message-ID: <2431472.g0LapiKI9t@harvey> Someone successfully hooked up an Atmega MCU without differential gates (and so) to a DDR interface and got the DRAM chip to do something useful. You can also just use two IO pins instead of a differential gate, you just have to keep the transfer rates low enough, then you don't even need to tinker around with pull up and pull down resistors for compensating for the I/O pad resistance :-) Cheers -lev On Tuesday, July 20, 2021 9:18:35 AM WEST Hagen SANKOWSKI wrote: > Hello David. > > Long time ago, I had to connect an Altera FPGA with a DDR2 RAM. > It was a mess, do to an on-chip bug :-( > > BTW, as I still remember, at least a couple of signals are differential, > eg. Clock (CKx) and Data Select (DQSx), and needing balanced routing.. > > Sorry. > Hagen. > --- > "They who can give up essential liberty to obtain a little temporary > safety, deserve neither liberty nor safety." Benjamin Franklin (1775) > > Am 19.07.2021 16:06 schrieb David Lanzend?rfer: > > DRAM DDR3 without leveling IS an option. > > We don't need special pads and can just use the I/O pads :-) > > > > https://www.intel.com/content/dam/altera-www/global/ja_JP/pdfs/literature/ > > an/ an520.pdf > > > > There we go! =^_^=~~~~~ > > > > On Sunday, July 18, 2021 8:51:41 PM WEST Hagen SANKOWSKI wrote: > >> Meeting Minutes of the Mumble session today > >> =========================================== > >> > >> Participants: Devon, tatzelbrumm (partly), hsank, leviathan > >> > >> > >> Topics > >> ------ > >> > >> - (external) RAM > >> > >> While thinking about an RISC-V CPU demonstrator, we need memory for > >> loading an Operating System like Linux. > >> > >> Our first guess was for the demonstrator just to use external RAM > >> chips, > >> e.g. with HyperRAM, which has a quite simple interface and can be > >> driven > >> without LVDS-IO-Pads (which are still not available for us). > >> Unfortunately using a couple of them gets fast quite expansive. > >> > >> Using commercial available (and cheaper) DRAM nowadays is out of reach > >> for us - this chips using a proprietary interface called DDR2 or DDR3. > >> This interface needs differential IO-Pads (the LVDS we already > >> mentioned > >> above) and is critical about timing (in the meaning of different wire > >> length, wire resistance and so on). > >> > >> Without a PDK for a technology we can not design the analog stuff > >> inside > >> 'cause we still miss all the concrete values for the layers to > >> calculate > >> transistor and wire sizes. > >> > >> - alternative: internal hand-crafted RAM-cells > >> > >> Designing internal RAM cells, no matter whether dynamic RAM or static > >> RAM isn't possible without the analog values from the PDK.. > >> > >> - possible pathes to go > >> > >> * Reducing the Operating System to smaller memory footprints (e.g. > >> with > >> NetBSD) and soldering a reasonable amount of HyperRAM close to the CPU > >> > >> * Getting a PDK and design with a couple of iterations in silicon our > >> analog stuff (LVDS-IO-Pads or RAM-cells hand-crafted) 'till it works.. > >> > >> '''' > >> Note: if we'd start with an alien PDK we had to re-design the analog > >> stuff from ground up again for our LibreSilicon PDK again.. > >> '''' > >> > >> If you have some suggestions how to get out of our > >> chicken-and-egg-Problem, please drop us an email :-) > >> > >> > >> Regards, > >> Hagen > >> _______________________________________________ > >> Libresilicon-developers mailing list > >> Libresilicon-developers at list.libresilicon.com > >> https://list.libresilicon.com/mailman/listinfo/libresilicon-developersH -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From leviathan at libresilicon.com Wed Jul 21 00:52:30 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Tue, 20 Jul 2021 23:52:30 +0100 Subject: [Libre-silicon-devel] TSMC Message-ID: <23927266.7vSFSxx14k@harvey> So I wrote today to Kees Joosse from TSMC[1] and asked him whether they would accept an order from us sending them just the GDS2 files generated with the openly available design rules here[2]. I'll tell you IF I ever hear back from him... haha [1] https://www.linkedin.com/in/keesjoosse [2] https://git.libresilicon.com/?p=redmine/qtflow.git;a=blob_plain;f=tech/osu018/SCN6M_SUBM.10.tech;hb=HEAD -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From staf at fibraservi.eu Wed Jul 21 11:25:29 2021 From: staf at fibraservi.eu (Staf Verhaegen (FibraServi)) Date: Wed, 21 Jul 2021 11:25:29 +0200 Subject: [Libre-silicon-devel] TSMC In-Reply-To: <23927266.7vSFSxx14k@harvey> References: <23927266.7vSFSxx14k@harvey> Message-ID: <624307e0-561a-096a-efca-e2b67e4fab4a@fibraservi.eu> Op 21/07/2021 om 00:52 schreef David Lanzend?rfer: > So I wrote today to Kees Joosse from TSMC[1] and asked him whether they would > accept an order from us sending them just the GDS2 files generated with the > openly available design rules here[2]. > I'll tell you IF I ever hear back from him... haha MOSIS SCMOS design rules use other GDS2 layer numbering than TSMC so your gds2 will not be able to be manufactured by TSMC. It will also need other post processing before you will actually have a DRC compliant GDS2. I am considering supporting SCMOS compliant design with Chips4Makers though and process them in TSMC. greets, Staf. -- Chips want to be free. -------------- next part -------------- A non-text attachment was scrubbed... Name: OpenPGP_0x47D10429DCCF96DC.asc Type: application/pgp-keys Size: 1684 bytes Desc: OpenPGP public key URL: -------------- next part -------------- A non-text attachment was scrubbed... Name: OpenPGP_signature Type: application/pgp-signature Size: 495 bytes Desc: OpenPGP digital signature URL: From leviathan at libresilicon.com Wed Jul 21 22:54:23 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Wed, 21 Jul 2021 21:54:23 +0100 Subject: [Libre-silicon-devel] TSMC In-Reply-To: <624307e0-561a-096a-efca-e2b67e4fab4a@fibraservi.eu> References: <23927266.7vSFSxx14k@harvey> <624307e0-561a-096a-efca-e2b67e4fab4a@fibraservi.eu> Message-ID: <2075905.rmvk8WhAHb@harvey> Hi Staf Ok. That was, what I had asked TSMC among other things in my email, so thanks for answering this question. I don't really care who and how. All I wanna do is generate a layout, which I place and route and revision control on my public Git repository and I want a foundry which tapes it out. BTW: I did see that IMEC now works with you without even bothering to come back to me concerning my question whether it would be possible to at least give us access to some design rules, so that we can generate standard cells with them. If you could get us some design rules for IMEC, we could start generating standard cells and synthesize some test chips for this process... THAT would be interesting. Cheers -lev On Wednesday, July 21, 2021 10:25:29 AM WEST Staf Verhaegen (FibraServi) wrote: > Op 21/07/2021 om 00:52 schreef David Lanzend?rfer: > > So I wrote today to Kees Joosse from TSMC[1] and asked him whether they > > would accept an order from us sending them just the GDS2 files generated > > with the openly available design rules here[2]. > > I'll tell you IF I ever hear back from him... haha > > MOSIS SCMOS design rules use other GDS2 layer numbering than TSMC so > your gds2 will not be able to be manufactured by TSMC. It will also need > other post processing before you will actually have a DRC compliant GDS2. > > I am considering supporting SCMOS compliant design with Chips4Makers > though and process them in TSMC. > > greets, > Staf. -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From ludwig.jaffe_gmail at openhardware.de Mon Jul 19 17:49:00 2021 From: ludwig.jaffe_gmail at openhardware.de (Ludwig Jaffe) Date: Mon, 19 Jul 2021 17:49:00 +0200 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: <2198090.IbNUyZpdlT@harvey> References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> <2198090.IbNUyZpdlT@harvey> Message-ID: <9DB7BBF1-C929-4287-BCAF-D85E1AC9F44E@openhardware.de> No, bit banging with ram, no way! I had enough problems with a company whiche used gpio bit banging with a dsp )to read a fast ADC (What you dont fetch gets overwrittwn.) I On July 18, 2021 9:39:53 PM GMT+02:00, "David Lanzend?rfer" wrote: >Hi >So today we've been talking about ways around having to use DDR3/DDR4 >interfaces for external memory of a potential SoC but as it turns outs, >all >our candidates like HyperRAM or MRAM are out of the window because >of the prices. >As usual I came back to the question "is it possible to do this with an >AVR?" >which usually helps me at fixing such problems and I came across those >projects here: >https://www.circuitlake.com/interfacing-dram-memory-with-avr.html >https://github.com/jnk0le/AVR-DRAM >Turns out that it's possible to speak to DRAM over a DDR3 without a >special >controller, just over GPIO. >They got an Atmega to access a Hitatchi M5M44800. >The RAM access will be slow, but we don't need to know about the analog >properties of the process in order to achieve this. >I will probably implement this for my test SoC on a CPLD. >Hagen will explain more in the follow up/minutes. > >Cheers >-lev > >On Saturday, July 17, 2021 11:49:14 AM WEST Hagen SANKOWSKI wrote: >> Hello List! >> >> This is our weekly announcement for the next Mumble Sessions on >Sunday >> >> 2021-07-18 @ 18:00 UTC. >> >> Please join us as usual at our Mumble Server murmur.libresilicon.com >at >> Port 64738, the Channel is IC. >> >> We like to follow-up our topics from mumble sessions before. >> >> Regards, >> Hagen. >> _______________________________________________ >> Libresilicon-developers mailing list >> Libresilicon-developers at list.libresilicon.com >> >https://list.libresilicon.com/mailman/listinfo/libresilicon-developers > > >-- >(\__/) >(='.'=) This is Ninja Bunny. >(")_(") >Copy and paste Bunny into your >signature to help him gain world domination > >_______________________________________________ >Libresilicon-developers mailing list >Libresilicon-developers at list.libresilicon.com >https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- Sent from my Android device with K-9 Mail. Please excuse my brevity. -------------- next part -------------- An HTML attachment was scrubbed... URL: From leviathan at libresilicon.com Thu Jul 22 06:47:05 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Thu, 22 Jul 2021 05:47:05 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: <9DB7BBF1-C929-4287-BCAF-D85E1AC9F44E@openhardware.de> References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> <2198090.IbNUyZpdlT@harvey> <9DB7BBF1-C929-4287-BCAF-D85E1AC9F44E@openhardware.de> Message-ID: <101686496.fYCxCAAIUa@harvey> This isn't a problem with DRAM, it delivers values after you wrote the address and toggled the right bits and as long as you don't change anything, the DRAM has no reason to do something else, so I think I give hooking up some DDR3 RAM to an ICE40 a try :-) On Monday, July 19, 2021 4:49:00 PM WEST Ludwig Jaffe wrote: > No, bit banging with ram, no way! > I had enough problems with a company whiche used gpio bit banging with a dsp > )to read a fast ADC (What you dont fetch gets overwrittwn.) > > I > > On July 18, 2021 9:39:53 PM GMT+02:00, "David Lanzend?rfer" wrote: > >Hi > >So today we've been talking about ways around having to use DDR3/DDR4 > >interfaces for external memory of a potential SoC but as it turns outs, > >all > >our candidates like HyperRAM or MRAM are out of the window because > >of the prices. > >As usual I came back to the question "is it possible to do this with an > >AVR?" > >which usually helps me at fixing such problems and I came across those > >projects here: > >https://www.circuitlake.com/interfacing-dram-memory-with-avr.html > >https://github.com/jnk0le/AVR-DRAM > >Turns out that it's possible to speak to DRAM over a DDR3 without a > >special > >controller, just over GPIO. > >They got an Atmega to access a Hitatchi M5M44800. > >The RAM access will be slow, but we don't need to know about the analog > >properties of the process in order to achieve this. > >I will probably implement this for my test SoC on a CPLD. > >Hagen will explain more in the follow up/minutes. > > > >Cheers > >-lev > > > >On Saturday, July 17, 2021 11:49:14 AM WEST Hagen SANKOWSKI wrote: > >> Hello List! > >> > >> This is our weekly announcement for the next Mumble Sessions on > > > >Sunday > > > >> 2021-07-18 @ 18:00 UTC. > >> > >> Please join us as usual at our Mumble Server murmur.libresilicon.com > > > >at > > > >> Port 64738, the Channel is IC. > >> > >> We like to follow-up our topics from mumble sessions before. > >> > >> Regards, > >> Hagen. > >> _______________________________________________ > >> Libresilicon-developers mailing list > >> Libresilicon-developers at list.libresilicon.com > > > >https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From pg at futureware.at Sat Jul 24 21:38:53 2021 From: pg at futureware.at (Philipp =?iso-8859-1?Q?G=FChring?=) Date: Sat, 24 Jul 2021 21:38:53 +0200 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: Hi, What about "outsourcing" the memory controller over HyperRam? If we can do HyperRam, we could have a controller that translates HyperRam to DDR2/DDR3? Our CPU <-> HyperRam <-> Controller <-> DDR2/3 <-> DRAM chips Just an idea... Best regards, Philipp G?hring From leviathan at libresilicon.com Sat Jul 24 21:52:41 2021 From: leviathan at libresilicon.com (David =?ISO-8859-1?Q?Lanzend=F6rfer?=) Date: Sat, 24 Jul 2021 20:52:41 +0100 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-07-18 @ 18:00 UTC In-Reply-To: References: <75381fe5-19e2-3e41-ccf1-d76d3592821f@posteo.de> Message-ID: <3895201.dxGrrT622t@harvey> Hi The thing is that I wanna reduce the amount of proprietary IP on the PCB. I also considered the solution of making a simple converter, which basically contains only a DDR3/4 controller as well as a HyperRAM interface, but considering the overhead, it might actually be more practical to just try to use the DRAM over bit banging. It has been done already on FPGAs without specialized pads and it seems to be working, just without the maximum transfer rates. However, the solution over bitbanging probably is still the better solution IMHO, because it doesn't have the overhead of yet another component in between. Cheers -lev On Saturday, July 24, 2021 8:38:53 PM WEST Philipp G?hring wrote: > Hi, > > What about "outsourcing" the memory controller over HyperRam? If we can do > HyperRam, we could have a controller that translates HyperRam to DDR2/DDR3? > > Our CPU <-> HyperRam <-> Controller <-> DDR2/3 <-> DRAM chips > > Just an idea... > > Best regards, > Philipp G?hring > _______________________________________________ > Libresilicon-developers mailing list > Libresilicon-developers at list.libresilicon.com > https://list.libresilicon.com/mailman/listinfo/libresilicon-developers -- (\__/) (='.'=) This is Ninja Bunny. (")_(") Copy and paste Bunny into your signature to help him gain world domination From hsank at posteo.de Fri Jul 30 12:25:54 2021 From: hsank at posteo.de (Hagen SANKOWSKI) Date: Fri, 30 Jul 2021 10:25:54 +0000 Subject: [Libre-silicon-devel] Announcement - Mumble session on Sunday 2021-08-01 @ 18:00 UTC Message-ID: Hello List! This is our weekly announcement for the next Mumble Sessions on Sunday 2021-08-01 @ 18:00 UTC. Please join us as usual at our Mumble Server murmur.libresilicon.com at Port 64738, the Channel is IC. We like to follow-up our topics from mumble sessions before. Regards, Hagen.