Hello Everyone,
Today I figured out how to extract the drain current of the "real" PMOS from the currently available "leaky" measurements. The process is:
1. Take "thermally_compensated". 2. Compute the slope of the curve (i.e. leakage conductance) by averaging dY/dX between -0.5 and 0V (where "real") drain current is expected to be zero. 3. Based on that, calculate the D-G leakage current (linear resistive case). 4. Subtract the leakage from the measurement data.
[image: image.png]
The results show clearly a quadratic Id-Vgs behavior and a Vth around 0.6V. The spreadsheet containing the calculation is attached.
According to David, this was taken at a PMOS L10/W10 cell. Unfortunately, for the NMOS results, the instrument went off-scale around Vgs=0V, so the neccessary fix points cannot be acquired.
Regards, Ferenc
