Hello Everyone,
As per the last mumble session, my recommendations for debugging are the following:
Test subject: a native NMOS from the nmos table (no isolation/HV/etc., as only the basic layers were done). Specific measurements: - Diode characteristization (V-I curve) between source-bulk, while all other terminals left floating. Aim: check metal1 and contact continuity, check doping. Expected result: diode-like behavior. Possible failures: linear I-V curve (faulty doping), no current flows at all even when source is more negative than bulk (broken metal1, broken contact) - Diode characteristization (V-I curve) between drain-bulk, while all other terminals left floating. same as above. - V-I curve between source-drain, while gate and bulk tied to source (not to be performed if poly proves to be broken). Aim: check if end of the poly gate is indeed extending over fox edge (concern due to unexpected fox over-etch). Expected result: no current flows while drain is more positive than source. Possible failures: linear I-V curve (not enough overlap causes "bridging" between S-D).
The same may be done on a PMOS as well (just with opposite polarities).
Regards, Ferenc
On Sat, Jan 12, 2019 at 3:24 PM Hagen SANKOWSKI hsank@posteo.de wrote:
Hello List!
Just a small reminder for our next Mumble Sessions on this Sunday, January 13 at 21.00 o'clock Hong Kong Time.
Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC.
On the agenda are (at least) this topics
- test wafer status
- analog design stuff
- other stuff around libre silicon
Happy to hear from you! Hagen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel