On Wednesday, February 6, 2019, Staf Verhaegen <staf@fibraservi.eu> wrote:

Luke Kenneth Casson Leighton schreef op di 05-02-2019 om 07:34 [+0000]:

On Tuesday, February 5, 2019, Luke Kenneth Casson Leighton <lkcl@lkcl.net> wrote:

Hi best place to ask,

Have forgotten the name of a company that has a sea of gates high end ASIC, you get to do only the one mask, the via layer. Does anyone know the company? It is apparently supported by libre design tools.

So sorry, um I found it: https://www.easic.com/ products/28-nm-easic-nextreme-3/

They are now Intel and not interested in low to medium volume.

Ok good to know

Second, somewhere in this talk https://youtu.be/zXwy65d_tu8 is mentioned an open analog design project, does anyone know what that project is?

Haven't found this one yet

The VIA programmable analog company I know of is Triad Semiconductor with their configurable IC Technology <https://www.triadsemi.com/vca-technology/>.

That's a useful one as well. However the question was more libre. Are there any *libre* analog ASIC projects around, doing PLLs, DDR detection, differential pairs, and so on? greets,

Staf.

-- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

Hello All, Just some thoughts on the topic: - The architecture of Lattice PAC is very purpose-specific, tailored for control-loop, monitoring and power management tasks. It is in no way a general-purpose analog platform. - Triad VCA is a better approach on the technical side. However, it has its own drawbacks: 1. It is explicitly stated that the platform is patented, so using it easily results in vendor lock-in with a single source. 2. They seem to use "usual" fabs behind the set and don't seem to be interested in the "custom IC in single quantities for realistic end-user price" business (as free software can be recompiled by the user, free Si shall be re-tape-out-able by the end user) 3. The concerns mentioned by David also hold (hidden circuitry in pads, ...) - If a IC project exists that is analog and open-source and useful simultaneously: I don't think so. Analog designs are inseparable from the PDK and technology they were made for: a design made for an university or research process lacks the manufacturing capability that would be needed to be used for real-life volumes, while a design tainted by the PDK of a commercial process would be born secret (if everyone knows that R=Rsq*(L/W), and Rsq is secret, then any R,W,L triplets for that Rsq would also be secret). Regards, Ferenc On Wed, Feb 6, 2019 at 8:28 AM ludwig jaffe <ludwig.jaffe@gmail.com> wrote:

Hi all,

also lattice has programable analog which is an ic containing opamps, switched capacitor filters bandgap references and some analog muxes which are transfer gates I guess, and some programable resistors (mux and resistor on chip) and capacitors. They are called PAC, iirc.

Just look it up.

If we want such we can start with a bandgap some op amps like lm324 and a lot of transfer gates like cd4066. With a lot of pins we can connect external components and we may have on chip resistors and matched pair transistors in bipolar and junction fets .

Cheers

Ludwig

On Tuesday, February 5, 2019, Staf Verhaegen <staf@fibraservi.eu> wrote:

...

Luke Kenneth Casson Leighton schreef op di 05-02-2019 om 07:34 [+0000]:

On Tuesday, February 5, 2019, Luke Kenneth Casson Leighton < lkcl@lkcl.net> wrote:

Hi best place to ask, Have forgotten the name of a company that has a sea of gates high end ASIC, you get to do only the one mask, the via layer. Does anyone know the company? It is apparently supported by libre design tools.

So sorry, um I found it: https://www.easic.com/products/28-nm-easic-nextreme-3/

They are now Intel and not interested in low to medium volume.

Second, somewhere in this talk https://youtu.be/zXwy65d_tu8 is mentioned an open analog design project, does anyone know what that project is?

Haven't found this one yet

The VIA programmable analog company I know of is Triad Semiconductor with their configurable IC Technology. greets, Staf.

-- Send from mobile phone with autocorrection / autofill. Blame my phone for typos.

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Hi

Nice talk. But no, no glue which project he mention. Please ask Bunnie, I am very curious too. What Bunnie is talking about is a very old and well known manufacturing method and is called "gate arrays". Problems hereby are: a) The standard cells are still closed b) Unsuitable as soon as you wanna design anything beyond digital c) There can be a logger or anything in the pad cells and you wouldn't know d) Reverse engineering the chips you receive would also be a criminal offense.

-lev -- Best regards CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen