Hi,
I just found something in Sam Zeloof's latest design (08/2021) that I overlooked first and I'm not sure if it has been discussed here yet... He uses wafers which are pre-doped for p-wells, and gate oxide and polysilicon pre-applied without any mask. He then patterns, etches and n-dopes source/drain regions, using the poly as a mask and then adds "hard-baked photoresist as a dielectric" to separate the poly gate from the above metal layer. This requires some changes in the process and will only allow n-type transistors, but he completely avoids the problems with poly deposition AND doesn't have to grow field oxide -- so I'm actually not sure if he needs a high-temp furnace at all.
Link: top article on http://sam.zeloof.xyz/category/semiconductor/
Opinions?
Greetings, Martin
Hi We already have been looking at Sam's process flow a while ago and already noticed that he's "cheating", by using specialized wafers. However. My goal is to develop a full stack manufacturing process, without skipping essential parts. I rather wanna find alternative chemical recipes for growing poly and oxide which do not require military-grade poisonous gases :-)
Cheers -lev
On Saturday, February 5, 2022 3:34:52 PM WET Martin Geisse wrote:
Hi,
I just found something in Sam Zeloof's latest design (08/2021) that I overlooked first and I'm not sure if it has been discussed here yet... He uses wafers which are pre-doped for p-wells, and gate oxide and polysilicon pre-applied without any mask. He then patterns, etches and n-dopes source/drain regions, using the poly as a mask and then adds "hard-baked photoresist as a dielectric" to separate the poly gate from the above metal layer. This requires some changes in the process and will only allow n-type transistors, but he completely avoids the problems with poly deposition AND doesn't have to grow field oxide -- so I'm actually not sure if he needs a high-temp furnace at all.
Link: top article on http://sam.zeloof.xyz/category/semiconductor/
Opinions?
Greetings, Martin
Hi With a sputterer we could just sputter the silicon for forming the gates... What do you think?
Cheers -lev
On Saturday, February 5, 2022 3:48:57 PM WET David Lanzendörfer wrote:
Hi We already have been looking at Sam's process flow a while ago and already noticed that he's "cheating", by using specialized wafers. However. My goal is to develop a full stack manufacturing process, without skipping essential parts. I rather wanna find alternative chemical recipes for growing poly and oxide which do not require military-grade poisonous gases :-)
Cheers -lev
On Saturday, February 5, 2022 3:34:52 PM WET Martin Geisse wrote:
Hi,
I just found something in Sam Zeloof's latest design (08/2021) that I overlooked first and I'm not sure if it has been discussed here yet... He uses wafers which are pre-doped for p-wells, and gate oxide and polysilicon pre-applied without any mask. He then patterns, etches and n-dopes source/drain regions, using the poly as a mask and then adds "hard-baked photoresist as a dielectric" to separate the poly gate from the above metal layer. This requires some changes in the process and will only allow n-type transistors, but he completely avoids the problems with poly deposition AND doesn't have to grow field oxide -- so I'm actually not sure if he needs a high-temp furnace at all.
Link: top article on http://sam.zeloof.xyz/category/semiconductor/
Opinions?
Greetings, Martin
Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
Hi The more I think about it, the more it starts to look feasible. For the gate formation, we can just "abuse" the sputterer for depositing the silicon layer, and for the isolation, we can use the spin coater with a silicone solution and react it in the furnace into silicon oxide. I think I'll sit down and start working out the chemical formulas... would be easier, if I'd actually be a chemist tho... Haha Any chemists here on the mailinglist anyway?
Cheers -lev
On Saturday, February 5, 2022 3:56:45 PM WET David Lanzendörfer wrote:
Hi With a sputterer we could just sputter the silicon for forming the gates... What do you think?
Cheers -lev
On Saturday, February 5, 2022 3:48:57 PM WET David Lanzendörfer wrote:
Hi We already have been looking at Sam's process flow a while ago and already noticed that he's "cheating", by using specialized wafers. However. My goal is to develop a full stack manufacturing process, without skipping essential parts. I rather wanna find alternative chemical recipes for growing poly and oxide which do not require military-grade poisonous gases :-)
Cheers -lev
On Saturday, February 5, 2022 3:34:52 PM WET Martin Geisse wrote:
Hi,
I just found something in Sam Zeloof's latest design (08/2021) that I overlooked first and I'm not sure if it has been discussed here yet... He uses wafers which are pre-doped for p-wells, and gate oxide and polysilicon pre-applied without any mask. He then patterns, etches and n-dopes source/drain regions, using the poly as a mask and then adds "hard-baked photoresist as a dielectric" to separate the poly gate from the above metal layer. This requires some changes in the process and will only allow n-type transistors, but he completely avoids the problems with poly deposition AND doesn't have to grow field oxide -- so I'm actually not sure if he needs a high-temp furnace at all.
Link: top article on http://sam.zeloof.xyz/category/semiconductor/
Opinions?
Greetings, Martin
Libresilicon-developers mailing list Libresilicon-developers@list.libresilicon.com https://list.libresilicon.com/mailman/listinfo/libresilicon-developers
libresilicon-developers@list.libresilicon.com
-
David Lanzendörfer -
Martin Geisse