Hello David, Acc. to the last conversation, the following concerns are identified (some may be RTFM): - Step 8.3 equipment is incorrect - Also step 8.3, is a tunnel oxide of 40nm thick is thin enough, or we need thinner? - Between 13.8 and 13.9, a cleaning step seems to be missing - When are the drain/source implants driven in? Is the annealing during silicide formation sufficient for drive-in? - The implantation dose and acceleration for the wells and the base/emitter layers are the same. - Implant stop nitride is 40nm grown, but etching is only for 10nm. - Al etch time is for 600nm, but the metal layer is 620nm thick. Also, will the Al etcher pass trough Ti?
Regards, Ferenc
Hi So I fixed most of the stuff you've pointed out now. About the oxide thickness: We wanna avoid having a break through the oxide when reaching 40V or so. With 40nm we're pretty much at 40V for the breakthrough voltage. I don't know how much the gates of your high power transistors can take? But I guess they're also bound to the laws of physics. We would like to sell those chips to automotive manufacturers, so going below 40nm isn't really an option I'm afraid. I've added another annealing step for the p/n junction implants.
Cheers David
PS: Hagen and I got the same results for bright field and dark field mask requirements, so it seems alright. We're really close to ordering the mask set!
On Sunday, 4 November 2018 10:13:16 PM HKT Éger Ferenc wrote:
Hello David, Acc. to the last conversation, the following concerns are identified (some may be RTFM): - Step 8.3 equipment is incorrect
- Also step 8.3, is a tunnel oxide of 40nm thick is thin enough, or we need
thinner? - Between 13.8 and 13.9, a cleaning step seems to be missing
- When are the drain/source implants driven in? Is the annealing during
silicide formation sufficient for drive-in? - The implantation dose and acceleration for the wells and the base/emitter layers are the same. - Implant stop nitride is 40nm grown, but etching is only for 10nm. - Al etch time is for 600nm, but the metal layer is 620nm thick. Also, will the Al etcher pass trough Ti?
Regards, Ferenc
Hello, Good to know that bright/darkfield requirements are OK. I revised the changes on the process flow, it seems correct now, except the thickness of the tunnel oxide. We will still be OK at 40V even with significantly reduced tunnel oxide thickness, as we have the nitride and the (unchanged 40nm) gate oxide over it to withstand the electric field. Regards, Ferenc
On Tue, Nov 6, 2018 at 2:38 PM David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Hi So I fixed most of the stuff you've pointed out now. About the oxide thickness: We wanna avoid having a break through the oxide when reaching 40V or so. With 40nm we're pretty much at 40V for the breakthrough voltage. I don't know how much the gates of your high power transistors can take? But I guess they're also bound to the laws of physics. We would like to sell those chips to automotive manufacturers, so going below 40nm isn't really an option I'm afraid. I've added another annealing step for the p/n junction implants.
Cheers David
PS: Hagen and I got the same results for bright field and dark field mask requirements, so it seems alright. We're really close to ordering the mask set!
On Sunday, 4 November 2018 10:13:16 PM HKT Éger Ferenc wrote:
Hello David, Acc. to the last conversation, the following concerns are identified
(some
may be RTFM): - Step 8.3 equipment is incorrect
- Also step 8.3, is a tunnel oxide of 40nm thick is thin enough, or we
need
thinner? - Between 13.8 and 13.9, a cleaning step seems to be missing
- When are the drain/source implants driven in? Is the annealing during
silicide formation sufficient for drive-in? - The implantation dose and acceleration for the wells and the base/emitter layers are the same. - Implant stop nitride is 40nm grown, but etching is only for 10nm. - Al
etch
time is for 600nm, but the metal layer is 620nm thick. Also, will the Al etcher pass trough Ti?
Regards, Ferenc
-- Best regards
CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen
Hello
Good to know that bright/darkfield requirements are OK.
Good.
I revised the changes on the process flow, it seems correct now, except the thickness of the tunnel oxide. We will still be OK at 40V even with significantly reduced tunnel oxide thickness, as we have the nitride and the (unchanged 40nm) gate oxide over it to withstand the electric field.
The standard transistors don't have Nitride, only SONOS flash has. Or do you suggest that we use SONOS gates for being tolerant to higher voltages at the pads? Hagen and I discussed the topic and we figured for the first MCU it's sufficient to just hook everything up to the external VDD/GND rails directly. For further releases we might wanna put an internal linear power regulator though. Maybe we can provide an external LM7805 and some level-shifters on the development board first and integrate it in a further release?
Cheers David
libresilicon-developers@list.libresilicon.com
-
David Lanzendörfer -
Éger Ferenc