Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much lower, which will give less losses in the device.
Cheers David
David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]:
Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much lower, which will give less losses in the device.
General comment is that resistance is not about power efficiency. Power efficiency is in CMOS related to the capacitances that are charged and uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you can go. Too high well resistance increases the risk for latch-up problems though.
greets, Staf.
Ok! Thanks a lot! I will update the document accordingly!
greets David
On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]:
Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much lower, which will give less losses in the device.
General comment is that resistance is not about power efficiency. Power efficiency is in CMOS related to the capacitances that are charged and uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you can go. Too high well resistance increases the risk for latch-up problems though.
greets, Staf.
You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)
We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor.
Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)
On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Ok! Thanks a lot! I will update the document accordingly!
greets David
On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]:
Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much
lower,
which will give less losses in the device.
General comment is that resistance is not about power efficiency. Power efficiency is in CMOS related to the capacitances that are charged and uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you can go. Too high well resistance increases the risk for latch-up problems though.
greets, Staf.
-- Best regards
CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
download these books:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter1.pdf
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter2.pdf and so on play with the links and download it.
http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uyemura_-_Cmos_Logi...
On Sun, Mar 4, 2018 at 3:03 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)
We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor.
Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)
On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Ok! Thanks a lot! I will update the document accordingly!
greets David
On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]:
Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much
lower,
which will give less losses in the device.
General comment is that resistance is not about power efficiency. Power efficiency is in CMOS related to the capacitances that are charged and uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you can go. Too high well resistance increases the risk for latch-up problems though.
greets, Staf.
-- Best regards
CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4005e/mi_blog/r/C...
On Sun, Mar 4, 2018 at 3:14 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
download these books:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_ f01/Notes/chapter1.pdf
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_ f01/Notes/chapter2.pdf and so on play with the links and download it.
http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P. Uyemura_-_Cmos_Logic_Circuit_Design_2002.pdf
On Sun, Mar 4, 2018 at 3:03 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)
We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor.
Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)
On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Ok! Thanks a lot! I will update the document accordingly!
greets David
On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]:
Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much
lower,
which will give less losses in the device.
General comment is that resistance is not about power efficiency. Power efficiency is in CMOS related to the capacitances that are charged and uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you can go. Too high well resistance increases the risk for latch-up problems though.
greets, Staf.
-- Best regards
CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hello Ludwig.
Well, we already dealing with that issue since 34c3 - so we already knowing all books you can google and even more..
The problem is - someone has to go through the stuff and understand whats happen there. Just throw in all books into the ring isn't sufficient.
In that case David already did a great job. If you like to contribute, look at the math he has here https://github.com/leviathanch/libresiliconprocess on the document.pdf file. We have to understand the pyhsics, the basics. More Eyeballing is greatly appreciated. So, punch the errors out of the document, annotate comments, this would be very helpful.
Hagen.
On 03/04/2018 09:15 PM, ludwig jaffe wrote:
https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4005e/mi_blog/r/C...
On Sun, Mar 4, 2018 at 3:14 PM, ludwig jaffe <ludwig.jaffe@gmail.com mailto:ludwig.jaffe@gmail.com> wrote:
download these books: http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter1.pdf <http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter1.pdf> http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter2.pdf <http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter2.pdf> and so on play with the links and download it. http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uyemura_-_Cmos_Logic_Circuit_Design_2002.pdf <http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uyemura_-_Cmos_Logic_Circuit_Design_2002.pdf> On Sun, Mar 4, 2018 at 3:03 PM, ludwig jaffe <ludwig.jaffe@gmail.com <mailto:ludwig.jaffe@gmail.com>> wrote: You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities) We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor. Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on) On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer <david.lanzendoerfer@o2s.ch <mailto:david.lanzendoerfer@o2s.ch>> wrote: Ok! Thanks a lot! I will update the document accordingly! greets David On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote: > David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]: > > Hi > > Should I diffuse the p-well instead of just ion implanting it? > > It will take another 12 hours, but the on-resistance would be much lower, > > which will give less losses in the device. > > General comment is that resistance is not about power efficiency. Power > efficiency is in CMOS related to the capacitances that are charged and > uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you > can go. > Too high well resistance increases the risk for latch-up problems > though. > > greets, > Staf. -- Best regards CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com <mailto:Libre-silicon-devel@list.libresilicon.com> http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel>
Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
https://sanjayachauwal.files.wordpress.com/2017/03/cmos_ digital_integrated_circuits.pdf
we need more such books. http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P. Uyemura_-_Cmos_Logic_Circuit_Design_2002.pdf
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1. 465.9904&rep=rep1&type=pdf
around page 1177 it looks very interesting https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4005e/mi_blog/r/C...
On Sun, Mar 4, 2018 at 3:15 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b400 5e/mi_blog/r/CMOS_Circuit_Design__Layout__and_Simulation__3rd_Edition.pdf
On Sun, Mar 4, 2018 at 3:14 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
download these books:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/ Notes/chapter1.pdf
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/ Notes/chapter2.pdf and so on play with the links and download it.
http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uye mura_-_Cmos_Logic_Circuit_Design_2002.pdf
On Sun, Mar 4, 2018 at 3:03 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)
We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor.
Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)
On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Ok! Thanks a lot! I will update the document accordingly!
greets David
On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]:
Hi Should I diffuse the p-well instead of just ion implanting it? It will take another 12 hours, but the on-resistance would be much
lower,
which will give less losses in the device.
General comment is that resistance is not about power efficiency.
Power
efficiency is in CMOS related to the capacitances that are charged and uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you can go. Too high well resistance increases the risk for latch-up problems though.
greets, Staf.
-- Best regards
CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
found something about 1um cmos. looks interessting: http://portal.unimap.edu.my/portal/page/portal30/Lecturer%20Notes/KEJURUTERA...
and more theory http://userweb.eng.gla.ac.uk/fikru.adamu-lema/Chapter_01.pdf 01->n
On Sun, Mar 4, 2018 at 3:26 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
https://sanjayachauwal.files.wordpress.com/2017/03/cmos_digi tal_integrated_circuits.pdf
we need more such books. http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uye mura_-_Cmos_Logic_Circuit_Design_2002.pdf
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.465 .9904&rep=rep1&type=pdf
around page 1177 it looks very interesting https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b400 5e/mi_blog/r/CMOS_Circuit_Design__Layout__and_Simulation__3rd_Edition.pdf
On Sun, Mar 4, 2018 at 3:15 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4 005e/mi_blog/r/CMOS_Circuit_Design__Layout__and_Simulation__ 3rd_Edition.pdf
On Sun, Mar 4, 2018 at 3:14 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
download these books:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/No tes/chapter1.pdf
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/No tes/chapter2.pdf and so on play with the links and download it.
http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uye mura_-_Cmos_Logic_Circuit_Design_2002.pdf
On Sun, Mar 4, 2018 at 3:03 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)
We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor.
Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)
On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Ok! Thanks a lot! I will update the document accordingly!
greets David
On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]: > Hi > Should I diffuse the p-well instead of just ion implanting it? > It will take another 12 hours, but the on-resistance would be much
lower,
> which will give less losses in the device.
General comment is that resistance is not about power efficiency.
Power
efficiency is in CMOS related to the capacitances that are charged
and
uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast
you
can go. Too high well resistance increases the risk for latch-up problems though.
greets, Staf.
-- Best regards
CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
more on process http://portal.unimap.edu.my/portal/page/portal30/Lecturer%20Notes/KEJURUTERA...
On Sun, Mar 4, 2018 at 3:30 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
found something about 1um cmos. looks interessting: http://portal.unimap.edu.my/portal/page/portal30/Lecturer% 20Notes/KEJURUTERAAN_MIKROELEKTRONIK/SEM/EMT362_ MIKROELECTRONICSFABRICATION/LECTURE%204AA%20-% 20PHOTOLITHOGRAPHY%20PROCESS%20FOR%201UM.PDF
and more theory http://userweb.eng.gla.ac.uk/fikru.adamu-lema/Chapter_01.pdf 01->n
On Sun, Mar 4, 2018 at 3:26 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
https://sanjayachauwal.files.wordpress.com/2017/03/cmos_digi tal_integrated_circuits.pdf
we need more such books. http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uye mura_-_Cmos_Logic_Circuit_Design_2002.pdf
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.465 .9904&rep=rep1&type=pdf
around page 1177 it looks very interesting https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4 005e/mi_blog/r/CMOS_Circuit_Design__Layout__and_Simulation__ 3rd_Edition.pdf
On Sun, Mar 4, 2018 at 3:15 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
https://www.u-cursos.cl/usuario/9553d43f5ccbf1cca06cc02562b4 005e/mi_blog/r/CMOS_Circuit_Design__Layout__and_Simulation__ 3rd_Edition.pdf
On Sun, Mar 4, 2018 at 3:14 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
download these books:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/No tes/chapter1.pdf
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/No tes/chapter2.pdf and so on play with the links and download it.
http://www.csun.edu/~acm31201/Class%20Work/ECE%20442/J.P.Uye mura_-_Cmos_Logic_Circuit_Design_2002.pdf
On Sun, Mar 4, 2018 at 3:03 PM, ludwig jaffe ludwig.jaffe@gmail.com wrote:
You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)
We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor.
Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)
On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer < david.lanzendoerfer@o2s.ch> wrote:
Ok! Thanks a lot! I will update the document accordingly!
greets David
On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote: > David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]: > > Hi > > Should I diffuse the p-well instead of just ion implanting it? > > It will take another 12 hours, but the on-resistance would be much lower, > > which will give less losses in the device. > > General comment is that resistance is not about power efficiency. Power > efficiency is in CMOS related to the capacitances that are charged and > uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you > can go. > Too high well resistance increases the risk for latch-up problems > though. > > greets, > Staf.
-- Best regards
CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
So, please go to the documents David already wrote, check the math, check the threshold calculation. This would help a lot!
At least I need to read about process technology as I forgot nearly all from my studies of electrical engineering, as I never needed it.
On Sun, Mar 4, 2018 at 3:37 PM, Hagen SANKOWSKI hsank@posteo.de wrote:
So, please go to the documents David already wrote, check the math, check the threshold calculation. This would help a lot! _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Awesome! The help would be so precious! If you could help extending the document that would be so fantastic! And if you could tune in to our weekly mumble session at least once a while that would also be so fantastic!
Thanks so much for your input so far!
I will go through the links tomorrow with another liter of coffee ;-)
Cheers David
On Monday, 5 March 2018 4:48:04 AM HKT ludwig jaffe wrote:
At least I need to read about process technology as I forgot nearly all from my studies of electrical engineering, as I never needed it.
On Sun, Mar 4, 2018 at 3:37 PM, Hagen SANKOWSKI hsank@posteo.de wrote:
So, please go to the documents David already wrote, check the math, check the threshold calculation. This would help a lot! _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel
Hi
So, please go to the documents David already wrote, check the math, check the threshold calculation. This would help a lot!
Yes! Please! Check my math! For instance, I just was going through the required thresholds for matching the logic levels of TTL and realized that we actuall have to lower the threshold of the PMOS device! (Me stupid) If we have a VDD=5V then of course in order to satisfy the condition of switching at 2V threshold would need to be somewhere around -3V! With 3.3V it only would need to be -1.3V So we could shift the threshold V_Tp to somwhat -1.2 ish Volts.
What do you think?
And no worries, it's a university stuff refresher for me as well. I'm having a never ending row of "Aha!"-experiences since I've started writing this document, in combination with an afterwards-low, where I'm having a feeling of being soooo dumb for having needed a whole day to look through it although it's sooo simple. You're welcome to join me on this path to enlightenment ;-)
Cheers David
Hello Ludwig.
Look at this Dual-Gate Mosfet Side [0]- especially the picture with the cross-view.
There are to transistores in series, this is the same layout as we are already using here [1]
So we can't avoid the problem, to add both Threshold-Voltages to each other. If we like to switch on both transistors the input signal has to have reach at least 2 times Vth..
[0] http://www.radio-electronics.com/info/data/semicond/fet-field-effect-transis... [1] https://commons.wikimedia.org/wiki/File:CMOS_NAND_Layout.svg
On 03/04/2018 09:03 PM, ludwig jaffe wrote:
You want to diffuse! All tools to reduce the on resistance are important because (x) better efficiency (x) better switching (R-C lowpass formed by on-resistance and parasitic capacities)
We need to read books / documentation about cmos processes. Dont do fancy stuff like trench FETs. Maybe, we should also do dual gate mos-fets or tripple-gate mos-fets as this allows us to build in AND or OR-Gates using physics: One gate charge is not enough to open the channel, 2 charges are enough. So you get an and gate with one transistor.
Its similar to the multi-emiter transistors in TTL which were PNP and the emiters were at the input to be pulled to gnd (pull at least one emitter to get the transistor switched on)
On Sun, Mar 4, 2018 at 12:37 PM, David Lanzendörfer <david.lanzendoerfer@o2s.ch mailto:david.lanzendoerfer@o2s.ch> wrote:
Ok! Thanks a lot! I will update the document accordingly! greets David On Sunday, 4 March 2018 7:22:18 PM HKT Staf Verhaegen wrote: > David Lanzendörfer schreef op zo 04-03-2018 om 00:39 [+0800]: > > Hi > > Should I diffuse the p-well instead of just ion implanting it? > > It will take another 12 hours, but the on-resistance would be much lower, > > which will give less losses in the device. > > General comment is that resistance is not about power efficiency. Power > efficiency is in CMOS related to the capacitances that are charged and > uncharged (e.g. P = C.f.V^2/2). The resistance determines how fast you > can go. > Too high well resistance increases the risk for latch-up problems > though. > > greets, > Staf. -- Best regards CEO, David Lanzendörfer Lanceville Technology 22A, Block2, China Phoenix Mansion, No.2008 Shennan Boulevard, Futian District, Shenzhen _______________________________________________ Libre-silicon-devel mailing list Libre-silicon-devel@list.libresilicon.com <mailto:Libre-silicon-devel@list.libresilicon.com> http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel <http://list.libresilicon.com/mailman/listinfo/libre-silicon-devel>
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