January 2019 - Libresilicon-developers

KiCAD VLSI design
by David Lanzendörfer 01 Feb '19

01 Feb '19

Hi folks So we need to approach the folks from CERN who design the KiCAD tool. What I would like to ask them is, whether they could take the code base of their PCB editor and hack it a bit, so that it can place and route VLSI designs as well. As far as I know KiCAD, it's actually already possible, by constraining the angles of the wires to 90 degrees and adding a grid lock for placement of components. What is missing though, is the ability to load gds libraries and to export it into GDS/Magic/DEF. It would be cool to have KiCAD for drawing analog circuits and then generating a VLSI layout from it, where you can drag and drop your components accordingly and connect it like in a PCB. Cheers David

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Reminder - next Mumble Session on Sunday (January 27, 2019) 13:00 UTC
by Hagen SANKOWSKI 26 Jan '19

26 Jan '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, January 27 at 9 p.m. Hong Kong Time - this is 13:00 UTC. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - test wafer status - the tool discussions last week - other stuff around Happy to hear from you! Hagen

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Reminder - next Mumble Session on Sunday (January 20, 2019) 9pm HKT
by Hagen SANKOWSKI 19 Jan '19

19 Jan '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, January 20 at 21.00 o'clock Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - test wafer status - analog design stuff - other stuff around libre silicon Happy to hear from you! Hagen

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Reminder - next Mumble Session on Sunday (January 13, 2019) 9pm HKT
by Hagen SANKOWSKI 14 Jan '19

14 Jan '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, January 13 at 21.00 o'clock Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - test wafer status - analog design stuff - other stuff around libre silicon Happy to hear from you! Hagen

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Announcement - LibreSilicon Twitter Account
by Hagen SANKOWSKI 06 Jan '19

06 Jan '19

Hello List! We are proudly like to inform you, that we are setting up a Twitter Account for the LibreSilicon Team also. So if you like, please follow us at https://twitter.com/LibreSilicon for short notice and pictures about the project progress. Best Regards, Hagen.

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Getting into LibreSilicon
by Hagen SANKOWSKI 06 Jan '19

06 Jan '19

==================================================== Welcome Everybody which is new on this mailing list! ==================================================== Version 0.0.1 For getting into LibreSilicon we like to compile some information for you. We are developing on github.com, all information is there. ----------- THE PROCESS ----------- The repository for the technology, means how to make structures on Silicon, you'll find under https://github.com/libresilicon/process Well, this repository is Work-in-Progress. The steps we are doing in the HKUST clean room you'll find under > process_mplementations > hkust in the process_hkust.pdf file. Every single step in long tables down to the machines. Please note, the numbers on the top left - this layer numbers are the same as in the GDS2 files for the Test Wafer. -------------- THE TEST WAFER -------------- A second (also important) repository for the Test Wafer (called PearlRiver) you'll find under https://github.com/chipforge/PearlRiver This repository is Work-in-Progress also. While we worked out the test structures on the wafer with a tool called Magic (originaly http://opencircuitdesign.com/magic) which we patched (patch https://github.com/libresilicon/magic-8.2) you should install Magic also to be show the structures graphical in a GUI. https://github.com/libresilicon/PearlRiver is a fork of the repository above. Under > Documentation > LaTeX you'll find the (still incomplete) documentation of all test structures which are located under > Library > magic This test structures are grouped together in tables and other forms which you'll see under > Layout > magic The README.md on top of the repository gives a help how to open the magic files. Since Magic is not the format foundries (and mask makers) usually understood, we deliver the common GDS2 files. This file format has the same role as Gerber for PCB designs. For viewing GDS2 file we recommend KLayout (https://klayout.de) This GDS viewer displays the layer just as numbers (which btw. the same as in the HKUST implementation document). ------------ MAILING LIST ------------ Please feel free to send your questions on this mailing list, someone of us will answer them. Sure. Your LibreSilicon Team.

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Reminder - next Mumble Session on Sunday (January 6, 2018) 21.00 HKT
by Hagen SANKOWSKI 05 Jan '19

05 Jan '19

Hello List! Just a small reminder for our next Mumble Sessions on this Sunday, July 8 at 21.00 Hong Kong Time. Please join us as usual at our Mumble Server with IP 109.109.202.102 at Port 64738, the Channel is IC. On the agenda are (at least) this topics - 35c3 report - test wafer status - analog design stuff - other stuff around libre silicon Happy to hear from you! Hagen

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Status request: ADC
by David Lanzendörfer 03 Jan '19

03 Jan '19

Hi One of the new faces at the table started to draw together an ADC with Magic. What's the status there? Cheers David

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Libre RISCV SoC (CPU VPU GPU)
by Luke Kenneth Casson Leighton 03 Jan '19

03 Jan '19

Hi ok so a quick update, some fascinating discussion underway on comp.arch over the past month, in which various people including Mitch Alsup have been educating me about multi issue architectures and how to do precise exceptions, branch speculation, and much more, using scoreboards based on the PROPER understanding of a 58 year old supercomputer called the Cray CDC 6600. Updates are at https://www.crowdsupply.com/libre-risc-v/m-class slightly behind, I have 7 outstanding to be reviewed and published. The SoC is to be quad core dual issue for 64 bit and quad issue for 32 bit vectorised instructions, 8 issue for 16 and 8 bit vectors. Vectors are variable length and predicated, being dropped directly onto the multi issue queue, rather than being a fake SIMD knockoff. 3D instructions will be added as necessary, identified already is the conversion from FP ARGB to 32 bit ARGB pixels, these to be done as vectors, vectorisation taken care of by the multi-issue execution engine, just like for every other instruction. Target performance is 5-6 GFLOPs, 100 M pixels/sec (1280x720 @ 25fps), 30 M triangles/s, if we exceed that, whoopee. Power budget 2.5 watts total system. VPU target, 720p decode, again only accelerate with custom ops where needed. It is a fascinating and scary microarchitecture that subdivides the register file into 4 32 bit banks of 2R1W cells with individual byte-write-enable lines, passthrough write to read ports in same cycle, where the 4 banks are split odd-even and hi32 lo32. Hence why it is dual issue for 64 bit and quad for 32 bit. A separate additional bus exists for operand forwarding, even though the writethru capability of the regfile also provides a type of operand forwarding. This because FMAC requires 3R1W normally, and the extra forwarding bus, if the FMACs are chained (src of 1 is dest of previous) will allow 4 32 bit FMACs per clock per 800mhz core, for a total of 12GFLOPs, 2x the target performance. Without the extra bus performance is halved as the banks of only 2R1W regfile becomes the bottleneck. I wont go into detail on how the 16 and 8 bit ops are handled, its too scary :) took weeks to work out. Overall going well, could use some help, we picked nmigen because it results in readable flexible code, no nonsense with #ifdefs and we have too much that needs OO programming to mess about with #ifdefs in native verilog. L. -- --- crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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