Libresilicon-developers May 2020

libresilicon-developers@list.libresilicon.com

4 participants
2 discussions

Badgood news on USA/TSMC/Huawei
by Éger Ferenc 18 May '20

18 May '20

Hello Everyone, Today I ran about two interesting articles (they are unfortunately in Hungarian, but they may be found in English somewhere, or use a translator): https://index.hu/gazdasag/2020/05/15/a_feher_haz_fokozza_a_nyomast_a_huawei… https://index.hu/techtud/2020/05/18/huawei_egyesult_allamok_amerika_kereske… Short warp-up: 1. USA government practically bans domestic and overseas licensees and users of US semiconductor IP and technology (including fab equipment) worldwide to do business with the Chinese, 2. Huawei's supplier TSMC stops accepting orders from Huawei, 3. TSMC opens new fab and relocates R+D to the USA for USD12bn. The bad side is that (besides the apparent restart of the Cold War) our experience with HKUST's CMP machine (no spare parts) may become the new global norm in the near future. The good side is that the bad side may undermine trust in the reliablity of US suppliers and devaluate their IP, while up-rating the value and importance of the open-source, worldwidely distributed silicon ecosystem that is not bound to to any corporation bound to a government (e.g. Kyrin is more or less based on ARM, whose licensing and subjection to US export control is an attack surface, while its direct competitor RISC-V is free of such restrictions), as companies may perceive either the US may say "You are the next who is locked out", or their non-US supplier may say next " I lock You out". Regards, Ferenc

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PearlRiver NG
by Philipp Gühring 10 May '20

10 May '20

Hi, Could we create larger PearlRiver like Testwafers, or is it already the largest size possible on our wafers? I would like to add some more structures on PearlRiver. Can I just enlarge it, or do I have to replace things? What would be the maximum size? According to David: "ideally we wanna make the next PearlRiver even smaller, rather than bigger, because the more dies you can fit on one wafer the better you can characterize issues with edge effects" What we could do is splitting the test structures across multiple test wafers based on the complexity level a lab can do. If a lab can't build polysilicon for instance, it's pointless for them to test polysilicon zener diodes." My idea at the moment is to build a Test Wafer generator which would help us there. Lets try to discuss this tomorrow in the Mumble call. Best regards, Philipp

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Libresilicon-developers May 2020