On Wed, Jun 27, 2018 at 10:00 AM, Hagen SANKOWSKI hsank@posteo.de wrote:
Assume that all this hiqh-speed busses using dedicated IO cells.
(as in, "not muxed")
As we are talking about muxing, this belongs to more-or-less standard CMOS/TTL leveled signals - no differential, no MIPI (with extra small swing), no SERDES signals (USB, SATA, Gbit Ethernet, RIO,..)
yep.
basically a pinmux is good for low-speed *digital* signals up to around 200mhz, possibly 300mhz if you're really lucky.
Assume a cut-off frequency (-3dB) of roundabout 150 MHz on Pads.
ok so that would explain why the single-data-rate variant of HyperRAM is a maximum of 150mhz. the DDR version goes up to a 166mhz clock (for a 300mhz total DDR rate), and requires an extra 13th pin and makes the clock into a differential pair.
i'm developing a $3 to $4 15x15mm 3W SoC, ludwig, not a $500 intel 150W completely impractical billion-transistor chip with a sale price of over $500.
Yes, an this chips has to fit together with a couple of another chips into the EOMA86 housing, known from PCMCIA cards.
PCB size 43x78mm, about 1/3 of that area for the PMICs, another 1/3 for memory ICs (less if using LPDDR3/4). it's *really* tight but doable.
l.