[Libre-silicon-devel] Gate sizes

Hi I now went through all the machines we're going to use and there is nothing which keeps us from having a feature size from 0.5 um in overall. Which means that the smallest an inverter could get is 2.5 um x 8.0um Also if someone feels like figuring out how to render this document into HTML feel free. I think it slowly becomes too big of a document to ship it as a PDF...

I'll drop some explenation on why the oxide etching with 0.5um isn't an issue as long as the mask is exposed properly in the document, but I think it's pretty clear, that there will be nothing stopping us from at least scaling down to 500nm pretty quickly as soon as we've got 1um working... At least from the lithographic and equipment point of view.

Cheers David