On Mon, Jun 25, 2018 at 7:55 PM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Hi I've now started wiring a RISC-V CPU generated with Rocket-Chip into a top level: https://github.com/leviathanch/SauMauPing1 However, for some reason it doesn't start trying to fetch instructions. I'll investigate tomorrow, for now I expect it to rain cats and dogs tonight and tomorrow as much as my head hurts right now. I'll relax now and get back tomorrow with lots of coffee.
Another important topic which came up when I tried to repurpose the memory controller from the North Point project: We will have to develop SRAM for our MCU or solder an external SRAM chip onto the board... like this one: https://github.com/freecores/zbt_sram_controller/blob/master/ZBTSRAM61NLP_NV...
a much faster option is xSPI (HyperRAM). it's less pins (12), runs at 150mhz for the non-DDR variant, and can do up to 150 mbyte/sec. if you want 300mbyte/sec, put in two HyperRAM interfaces.
edmund's team has a libre-licensed HyperRAM implementation done already.
i think it was micron who have 64 mbyte HyperRAM ICs commercially available.
now... if OpenRAM were to implement a libre-licensed HyperRAM chip instead of SRAM that would be REALLY interesting.
l.