Hi,
I just came back from my vacation.
I took a deeper look at the pad cell topic, and currently have the idea that we generate Pad cells the following way by seperating it into several pieces: The pad itself is generated with a generator where we just specify the size, and it takes the existing design rules for vias to stitch vias at the border. I developed that already. Then there is the logic area, there I am currently trying to write the specification for the logic area in our .cell format and using librecell lclayout to generate a layout for it, like the standard logic cells. Then we will need the frame power lanes, which will also be rather easy to generate. Then we need the big nmos and pmos transistors, I am not sure yet, whether we will enhance lclayout to be able to build them directly from spice netlist or whether we will use a special generator for them. In the end we have to connect and route all those components together. I am not sure yet how we will do that. Perhaps we can pre-specify the locations for lclayout then we could use a rather fixed routing, or we perhaps we need a router to do the job. Theoretically the pad cells should be done then, but perhaps some more stuff will need to be added.
Can anyone of you prepare ngspice spice tests for the pad cells that tests functionality and ESD resistance?
Best regards, Philipp