Hi
So, please go to the documents David already wrote, check the math, check the threshold calculation. This would help a lot!
Yes! Please! Check my math! For instance, I just was going through the required thresholds for matching the logic levels of TTL and realized that we actuall have to lower the threshold of the PMOS device! (Me stupid) If we have a VDD=5V then of course in order to satisfy the condition of switching at 2V threshold would need to be somewhere around -3V! With 3.3V it only would need to be -1.3V So we could shift the threshold V_Tp to somwhat -1.2 ish Volts.
What do you think?
And no worries, it's a university stuff refresher for me as well. I'm having a never ending row of "Aha!"-experiences since I've started writing this document, in combination with an afterwards-low, where I'm having a feeling of being soooo dumb for having needed a whole day to look through it although it's sooo simple. You're welcome to join me on this path to enlightenment ;-)
Cheers David