27 Jun
2018
27 Jun
'18
7:28 p.m.
Hi all I've now managed to strip away the Xilinx/FPGA specific configuration quirks and only produce a plain Verilog core which is platform agnostic: https://github.com/libresilicon/SauMauPing1/tree/master/builds Next steps are: * Wire all the peripherals out * Wire a GPU in there. For the GPU I'd prefer either Verilog (because of the Yosys support) or Chisel/Scala (Generates Verilog) Cheers -lev