Hi Staf I've now started to add content to the design rule chapter. The lithography limits us to 0.5um or higher with its minimum line spacing. I'm now reworking the choice and parameters of all the machines and will add the design rules in iteratively over the next few days.
I'm working a lot on this, but a day has only so many hours and I also need to sleep and so :-)
I hope to hear from many people on this list on Sunday 9pm Hong Kong time!
Cheers David
On Saturday, 10 March 2018 4:04:19 AM HKT Staf Verhaegen wrote:
David Lanzendörfer schreef op za 10-03-2018 om 01:35 [+0800]:
Can you folks think of any more test structures for the test-section besides
plain NMOS/PMOS and different caps and resistors using all the different layers?
A good exercise is to make the design rules chapter concrete with real values in them. For each of the rules determine what actually is the cause of this design rule (litho, etch, physics, ...) and then think about test structures to check if you meet the design rule in practice.
greets, Staf.