On Wed, 2019-05-01 at 10:44 -0400, ludwig jaffe wrote:
David, very brave work you do. We should find a business case to be able to collect money on a crowd funding platform like kickstarter.com
So we *need* a product and a road map. The product needs to be catchy and address needs of a geek.
Hi !
I am very new to this group, so please forgive if I am asking something that has been discussed already.
1. Do you guys have a standard cell library for this fab ?
2. Whats the smallest features size that can be supported ?
3. Can this chip be mixed analog/digital ?
4. Do you have any IP for this fab, like a SERDES for example ?
5. Is there any NRE ?
6. What is the wafer size ?
7. What is the wafer cost ?
8. Is there a die size limit ?
9. What packaging is available to you ?
I am trying to grasp what the boundaries of our imagination should be for proposing a "test chip".
I think it can be very easy to get funding for the right chip.
Best Regards, rudi =============================================================== Rudolf Usselmann, ASICS World Services, LTD, www.asics.ws Your IP Partner: SAS 12G, SATA-3, USB-3, SD/MMC/SDIO, FEC, etc.
The agony of poor quality remains long after the joy of low cost has been forgotten
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