[Libre-silicon-devel] STA and Simulation in a workflow

Hello List, this question comes in two parts and is for hardware designers: In the Alliance CAD System there is a tool called `asimut`, which does VHDL simulation and is executed after each step in the workflow basically. Is there an equivalent simulation tool in `qflow` or is it comparable to `ng-spice`? Would you execute `ng-spice` after each step in a hardware design flow? The second question is about finding an equivalent STA tool to `vesta`. STA is performed after Placing and then again after Routing, is this correct? I cannot find a similar tool in the Alliance CAD System but it is necessary for a complete silicon flow. Kind regards, Andreas Westerwick