Hello List, Hello David.
On 03/12/2018 06:41 PM, David Lanzendörfer wrote:
I now went through all the machines we're going to use and there is nothing which keeps us from having a feature size from 0.5 um in overall. Which means that the smallest an inverter could get is 2.5 um x 8.0um Also if someone feels like figuring out how to render this document into HTML feel free. I think it slowly becomes too big of a document to ship it as a PDF...
I'll drop some explenation on why the oxide etching with 0.5um isn't an issue as long as the mask is exposed properly in the document, but I think it's pretty clear, that there will be nothing stopping us from at least scaling down to 500nm pretty quickly as soon as we've got 1um working... At least from the lithographic and equipment point of view.
Thanks again for your effort!
Looks awesome - 3 technology nodes ahead. BTW, every next technology node is something like feature size of the node before divided by 2nd-root of two. This cut in half the area for the cell.
I think, we need this 1 um anyway for chips working on 5 Volt. This is also quite suitable for analog stuff like op-amps.
With 0.5 um only we are already in the 3.3 Volt domain, 5 Volt is to high for this small gates.
The best trade-off between 5 and 3.3 Volt was the node between (0.7 .. 0.8 um) - with different transistor sizing both voltages can be applied.
Currently I do not like to mix-up different voltages on the same chip - for instance by using 5 Volt at the IO-Ring and 3.3 Volt in the core area for all standard cells. This challenge we get soon with lower voltages for core area while staying compatible with outside-the-chip world with higher voltages.