7 Mar
2019
7 Mar
'19
12:44 p.m.
Hi all Today we've prepared the wafer for the RTP steps we're going to perform. If successful it will reduce the resistance of the polysilicon from a few Mega-Ohm to a few 100 Ohm per square. This is a required step on our way to provide FETs with a threshold voltage of 0.8V/-0.8V I'll update you tomorrow and we will discuss the results on Sunday.
Wish Victor and me luck tomorrow!
Cheers David