On 03/13/2018 11:13 AM, David Lanzendörfer wrote:
Hi So I'd say we for now indeed just do 1um and then just run a 500nm node on 3.3V only for SoCs and thelike.
After all, these SoCs and CPUs usually get a 3V3 rail from the ATX power supply anyway.
But yeah, if 5V tolerance is required in 500nm technology we will have to use the l=1um transistors from the 1um technology within the l=500nm technology for the buffer transistors.
Maybe we make "modular pad cells" which can be modified to provide 3V3 instead of 5V as well to the internal logic? Or maybe we just will have to modify our pad cells for the 500nm technology and require two power supplies, one for IO and one for internal circuitry? Or maybe have only one VDD and then a lot of linear voltage regulators built into the CMOS chips?
I'll think about that.
Unified IO-Cells should not be an issue as - transistor sizes in Pad-Cells only depends on current they have to drive outside and the ESD protection diodes; - there limitation in size is and will be the pad size with approx. 90..100um by 90..100um itself.
This is decoupled from our feature size. So, we can design IO-Pad-Cells with unified size, which applicable on all our technology nodes. In the end, the layouter will choose the Voltage-Supply-Cell he/she/it needs out of 5Volt, 3.3Volt or even lower cells.
Voltage regulators are quite ugly while taking a lot of area and spreading heat into the die. And, we do not have transformers on die.