On Wed, Jun 27, 2018 at 9:40 AM, Hagen SANKOWSKI hsank@posteo.de wrote:
Hello Luke.
On 06/27/2018 09:38 AM, Luke Kenneth Casson Leighton wrote:
in terms of price, performance and power budget, yes. if you look up the numbers (triangles/sec, pixels/sec, power usage, die area) you'll find it's really quite modest. nyuzi right now requires FOUR times the silicon area of e.g. MALI400 to achieve the same performance as MALI400, meaning that the power usage alone would be well in excess of the budget.
5 years back I got the chance during a freelancing work to get a deeper look into the MALI implementation in Verilog.
I think, we should become better than that crappy^H "legacy" code. There are very, very long combinatorial pathes, which are limiting the working frequency significant. This worst-case pathes are going over a lot of adder stages regarding the address translation logic.
IMHO, our goal should beat the mali and similar cores.
for the first version it's really not a high priority. low-power is far more important. with power being a square law on size, high-frequency clock rates become a bit of a problem. much better to put in double the hardware at half the speed and gain a 2x reduction in power consumption. 3D tiling is inherently parallelisable so it's not an issue.
In this arcitecture, the GPU, the CPU and the peripherals are all on the same AXI4 shared memory bus. They all have access to the same shared DDR3/DDR4 RAM. So as a result the GPU will use AXI4 to write directly to the framebuffer and the rest will be handle by SoC.
BTW, AXI4 is somehow open, but ARM has patented stuff on that. Please prefer a really free and open System-on-Chip Bus like Wishbone. And yes, I know, Wishbone does not have a streaming feature like AXI4..
i know of a commercial product that put the vga_lcd code into production. it used wishbone. it failed to reach speeds beyond 1024x768 @ 55hz, 15bpp.
also, AC97 is required and to do that efficiently and effectively AXI4 is necessary.
l.