Hello Andreas,
This is also to ask what is the role of `icarus verilog` in a `qflow`-based workflow and when a designer wishes to use it and what is a common reasoning for that.
Normally a digital flow would not use ng-spice, although qflow is able to make an efficient ng-spice simulation through the use of "xspice", and generates an xspice netlist.
I'm not sure what is the point of running simulations during a digital flow. I guess if you have a testbench that generates an output that can be parsed to determine if the simulation passes or fails, then you can run a simulation after any digital flow step that modifies the netlist to make sure that the modification has not caused the simulation to fail.
When running qflow, I normally run a simulation on the final netlist to make sure it works, but as I don't have any specific definition for a pass/fail testbench, qflow does not do this automatically.
---Tim
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