Hi Fixed it. Was really a piece of pwell exactly under metal1. Someone apparently has applied a piece of the metal on top of pwell to his rectangle when drawing these transistors ;-)
Fixed, commited and pushed
Please have another look. If we don't find anything anymore I'd say we order.
Cheers David
On Wednesday, 21 November 2018 2:14:56 PM HKT Hagen SANKOWSKI wrote:
Hello.
On 11/20/18 11:53 AM, David Lanzendörfer wrote:
I've now rendered a new GDS2 file with all the changes suggested by you folks. I fixed the last details and now don't see anything extraordinary anymore. Can you have a look at the output and see whether you spot an error I missed? https://github.com/libresilicon/PearlRiver/blob/master/Layout/gds/PearlRi ver_die.gds
I still miss the fix for NMOS W40 transistors.
Yesterday I figured out, that almost all NMOS W40 transistors have a suspect rectangle on STI layer (GDS layer #6) on Bulk contacts. This rectangle goes with metal. But all other transistors, whether PMOS nor NMOS does not have this rectangle.
If this make sense, to open STI just before the metal goes downto bulk, I would expect this opening window also on *all* other transistors. If it make no sense, we should remove this rectangle for NMOS_W40_L20, NMOS_W40_L10, NMOS_W40_L5 and NMOS_W40_L2 instead.
Unfortunately I couldn't figure out, where this suspect rectangles cames from. In Magic all stuff looks fine.
Do we have an issue here with GDS2 export?
@David: Could you look at this?
Regards, Hagen.