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On Thu, Jun 28, 2018 at 4:28 PM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
Hi After quiet a bit of research I had to realize that there isn't a single free DRAM controller code available.
there is.. .they're just damn hard to find.
They use the vendor specific closed IP cores...
yyup.
They're just using the vendor specific ones for the FPGA but don't have their own integrated in rocket-chip...
correct. and those typically don't have impedance matching / training on them, they assume fixed 40 ohms impedance, so if you build a PCB with that specific FPGA where the layers don't match up correctly to get the exact impedance on transmit and receive that the *specific* DRAM requires, you're absolutely screwed.
this is why you can only use *specific* SO-DIMMs and DRAMs with specific FPGAs.
Like for Xilinx they use the proprietary of theirs and so on. No one has bothered writing an actually free DRAM controller for DDR3/DDR4
DDR3 yes (see below).
in chisel
no and i'm not hugely enamoured with chisel, so no great loss there.
That's also most likely why SiFive didn't publish their actual code from which they've made the chips....
yyup.
ok so here's some links: https://github.com/enjoy-digital/litedram http://libre-riscv.org/shakti/m_class/DDR/ (hmm must update that) http://bugs.libre-riscv.org/show_bug.cgi?id=21 https://www.ohwr.org/projects/ddr3-sp6-core/wiki/wiki
so there *is* an actual DDR3 controller *and* there is symbioticaeda who have an LPDDR3 PHY which they're happy to make libre given the right price.
there's one other DDR3 controller that i know of, unfortunately it's GPL licensed.
l.