On Tue, Jun 26, 2018 at 11:24 AM, Hagen SANKOWSKI hsank@posteo.de wrote:
- also the input and output really need *automatic* level-shifting,
built-in to the IO cell. so whilst there is a VDD for driving the pad (and setting the CMOS threshold levels for input), there is *also* a need for an IO VREF. this is *important*. the input and output needs to be CMOS push-push (standard logic) whilst the IO pad needs to be switchable between OD and PP.
This comes to the list as soon as our technology node gets smaller. Currently we plan 1um with 5 Volt only. But next node with 0.5um should handle 5 Volt as 3.3 Volt. And so we do need this IO-Banking concept I am very familiar with from FPGAs.
as mentioned previously i have been told by a university that they are happy to put forward libre (and only libre) designs into actual silicon at zero charge. it's a 180nm fab.
- the ability to protect itself from *being* over-driven when in
input mode is not strictly necessary (over-voltage tolerance e.g. 5V tolerance when VDD is well below that) but would be nice to have as an option (two variants: one for ECs which need 5V tolerance and one for SoCs where it's not).
This topic and the topic before are aware by the ESD protection stuff.
ah ESD protection i understand to be completely different. basically a non-tolerant 3.3v design if fed with a sustained 5.0v input feeds that 5.0v signal *directly* into the logic, damaging pretty much everything in the process. that's *not* the same as feeding 5,000 volt static charge shocks. i don't precisely recall the circuit details but 5.0v tolerance in a 3.3v design would involve some... extra diodes or extra MOSFETs (damn big ones, hence the likely reason why they would be avoided in high-speed designs)
So, do you like to provide us (or me?) a list of requirements / features your embedded SoC really needs, which are nice to have and which are to avoid?
documented here:
http://libre-riscv.org/shakti/m_class/
i need to update it as i've managed to track down an LPDDR3 PHY (USD $300k), and also HyperRAM (upcoming JEDEC xSPI).
I'll keep an eye on this new hyped HyperRAM.
it's just quad spi with 4 extra data lines. real simple.
the project that i'm working on needs a 512 mbyte DRAM, to be made in a minimum of 110nm (which is where you can get up to 400mhz double data-rate). twin 128 mbyte DRAMs would do fine, as probably would four 64 mbyte DRAMs (in a pinch).
Any RAM, in principle, is a good technology driver while containing big regular structured areas. Do you now this https://github.com/VLSIDA/OpenRAM/blob/master/OpenRAM_ICCAD_2016_paper.pdf paper here?
i do now.
i have been promised (free, monetarily-zero-charge) access to a university's 180nm foundry *IF* and *ONLY* if the entire design is libre. if you can design a DRAM that can be tested for tape-out on 180nm which has a HyperRAM interface i *might* be able to justify putting it to the sponsor.
Until now I do not have experience with 180nm, so I am a little bit hesitating. Do you have more details for that?
i don't - i can find out in about 3-4 weeks time.
I understood this is a Europractice or Mosis Multi-Project-Wafer submission, isn't it?
i don't know. it's a fab at IIT Madras University, in Chennai.
Okay, about which time schedule we are talking?
get me a layout, i can send it to them immediately and see if they're serious about the offer.
Let's calculate: a 1-bit cell in 110nm would take - let's say - .5 by .5 um, multiplied with 512M (aka 536870912 cells) is 134217728 square microns. Doubled for back-stage stuff and IOs means 268435456 square microns at all - this are round about 16 x 16 mm if I am not completely wrong. Oh my god, this is huge!
is it? :) 16x16mm sounds perfectly fine to me :)
Okay, back from break, I got a good impression, where the problems are - size matters!
indeed :)
so... scaling that... 65nm would be... (65/110)^2 times the size, right? or if we want to just scale the 16mm by (65/110) that would be 9mm on a side. 45nm would be 6.5mm on a side (starting to get reasonably small... but also expensive).
DRAMs i understand the fabs actually tune the geometry to non-standard sizes, to get the best cost/yield/area. a numbers game.
l.