Hello Ludwig, Hello List.
On 1/3/19 7:45 AM, ludwig jaffe wrote:
A SAR would be interesting, especially if you add a multiplexer for the clock!
There is a clock-gate on the list for the Standard Cell Library already, which contains also the Latch behind the multiplexer (https://en.wikipedia.org/wiki/Clock_gating). Wikipedia miss the Latch btw :-o
May be we are able to have a PLL with a programmable frequency divider to generate higher Sampling frequencies that can be synchronized with external clock. If not, we would require an external PLL.
Well, Phase-locked Loops are very hard to design. IMHO the complexity is similar to ADCs. On the PearlRiver we already have 3 types of ring-oscillators, which are not stable enough while changing frequency with PVT (process-voltage-temperature) parameters. Here we use this effect to measure PVT influence..
Please feel free to design a PLL also. As soon as the technology nodes going down, and the internal feasible clock frequency rises over the cut-off frequency of any IO-Cells we are need them! Because we can not feed the internal clock from external anymore without a PLL.
I can provide everybody, who likes to design our first PLL, with a bunch of literature. But this guy should be an Analog one, not me as a Digital.
Regards, Hagen.