On Fri, Jul 6, 2018 at 6:43 AM, David Lanzendörfer david.lanzendoerfer@o2s.ch wrote:
The thing with this auto generated code is that it meshes everything into one verilog module. While Chisel produces nice hierarchical blocks, which makes it way easier to debug and understand. Additionally it basically assumes that "you want" to do an SoC so it kindof doesn't allow for easy extraction of the IP core... Additionally would we get stuck with an IP core with hard coded bus width and so on. Parameters are much nice, wouldn't you say?
why on earth didn't they put parameters into the python code?? oink??
About the silicon verification: We have to do this anyway, because we develop a new process here. And a iVerilog test bench seems good enough for me to start with.
cocotb automatically generates and then wraps the iverilog test bench and gives a python interface which can be interacted with by the python cocotb application.
i just do not understand why the hell people have been developing test benches in verilog. it's basically stone-age technology.
l.