Ah
And in case that sounded a bit religiously fanatic... ^^' I'm right now ducking scared about what will be the final condition from NLNet for getting the funding. So I'm basically at a point where I only can choose one or another option and hope for the best. In such cases, praying is a good option ^^'
-lev
On Monday, 23 December 2019 4:49:46 AM HKT David Lanzendörfer wrote:
Hi all I was too busy the last few weeks with working on a project for my best friend, but I've got the grant as well. I'm right now discussing about the conditions of getting the money transferred. The issue right now is, that they would prefer, that I work in an European lab, but I made the oath to myself that if I ever would step a foot back into Europe for longer than a short period of time, it would be either Greece (where the Eresian temple is located) or Portugal (where all the only good things in my life from Switzerland came from in one way or another). So now I'm discussing the possibilities of using the lab in Lisboa, which seems sufficiently equipped to facilitate our research. I'll see where it is leading me.
May Eris, the fairest of all goddesses, be with us. Thai Kallistai
-lev
On Sunday, 22 December 2019 2:15:12 PM HKT Hagen SANKOWSKI wrote:
Hello Luke.
On 12/22/19 7:04 AM, Luke Kenneth Casson Leighton wrote:
On Sunday, December 22, 2019, Hagen SANKOWSKI <hsank@posteo.de
mailto:hsank@posteo.de> wrote: Hello List!
On 12/22/19 1:51 AM, Luke Kenneth Casson Leighton wrote: > none aaat aaaaaalll. analog/mixed signals were veeery > specifically > and deeeliberately left *out* of the proposal entirely. > > the only analog/mixed signal designing that will occur is for DDR > GPIO > pads. even analog PLLs is highly likely to get left out, unless > someone can demonstrate that it's absolutely essential. It is. All the Pads have a cut-off frequency somewhere above 100 MHz. When we can run faster someday with smaller nodes, without a PLL, we could not tune up the clock frequency above this cut-off frequency.ok.
so, from somewhere, we need a libre licensed PLL. is one in development somewhere?
is it worth putting in an extra (small) NLNet grant application for?
The Issue I see - we have to bring back David into the Clean Room first. 'Cause PLLs are quite heavy analog Voodoo stuff and strongly depending on the technology they are using. IMHO we can not re-use a PLL developed for one technology on another technology.
So our goal has to have first the LibreSilicon PDK. Than, with this PDK we can design a PLL which could work for other LibreSilicon PDK users also.
Regards, Hagen.