Hi In order to accomplish what you described you would require a Liberty file of the 74HC logic blocks or so (e.g. 7408,7432,7400,7402,...). Then you could essentially synthesize your Verilog using standard logic gates in Yosys. Then you could convert your resulting BLIF file into a KiCAD netlist and load it within KiCADs PCB layout tool. There you can then map it to standard footprints, place and route it and make a PCB out of it which you can then manufacture and pick&place assemble.
Cheers David
On Monday, 26 November 2018 5:47:43 PM HKT Luke Kenneth Casson Leighton wrote:
hi,
are there any tools that will take verilog and generate something akin to a PCB "component" plus show a set of "unrouted nets"?
i would like to get a visual feel for what a design looks like, and a conversion of verilog to "blocks" is the easiest way i can think of.
l.