It's more for the purpose of designing analog IP cores which require manual "finesse" when being placed and routed. The actual place and route of the SoCs and MCUs will of course be done automatically using the nice place&route tool from Andreas.
-David
Also, again, the ability to recursively include PCB (or library parts) within PCBs aka Cells.
I did not reply earlier, the reason for this is firstly a full cell may have already been done (manual or auto routing) saving time and CPU , secondly, certain layouts may simply be far too complex or regular and may need to be generated either programmatically or by having blocks that the autorouter is permitted to place and route but not alter, thus saving time and also making the design easier to verify.