Hello Hagen,
Today I came across this nice RAM Generator:
https://github.com/VLSIDA/OpenRAM
Usually, all the Memories on the Die are generated. This means, a Vendor provides a Script to generate the memory-structure with address decoders, storage cells, output buffers, build-in tests etc.
I am familiar with this project and the two main groups involved with it, Matt Guthaus at U.C. Santa Cruz, and James Stine at Oklahoma State U. Integrating this into efabless and/or qflow is a very high priority for me. The main difficulty with integration is the need to design the analog components for each targeted process. There are no particular issues that I know of; it just takes a lot of time to do it.
If any of you wants to talk with Matt or James, I can make introductions.
Regards, Tim
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