Hi After quiet a bit of research I had to realize that there isn't a single free DRAM controller code available. They SiFive folks use the vendor specific closed IP cores... They're just using the vendor specific ones for the FPGA but don't have their own integrated in rocket-chip... Like for Xilinx they use the proprietary of Xilinx and so on.
No one seem to have bothered writing an actually free DRAM controller for DDR3/DDR4 in chisel so that one could actually build it as an asic. That's also most likely why SiFive didn't publish their actual code from which they've made the chips... Proprietary code, proprietary hard ware. Gotta swallow the thrown up back down every time I've gotta read the "freedom" word in the file paths of their repo and newsflashes right now...
Evaluated for you... we can't build this thing until we have designed our own DRAM controller... Anyway, I'm now doing a transplant and adapt their "Xilinx specific IP core" into my MIA702 version...[1] And the pain repeats on for every new board...
So good thing we've started already now evaluation. We'll gotta hire some additional folks to develop and push the missing IP cores needed for a tape-out to GitHub, as soon as we get there.
Cheers David
[1] https://item.taobao.com/item.htm?id=563964492619&_u=
On Thursday, 28 June 2018 3:28:21 AM HKT David Lanzendörfer wrote:
Hi all I've now managed to strip away the Xilinx/FPGA specific configuration quirks and only produce a plain Verilog core which is platform agnostic: https://github.com/libresilicon/SauMauPing1/tree/master/builds Next steps are:
- Wire all the peripherals out
- Wire a GPU in there.
For the GPU I'd prefer either Verilog (because of the Yosys support) or Chisel/Scala (Generates Verilog)
Cheers -lev