Catching up with this thread ...
On Sun, Jan 20, 2019 at 5:45 PM Luke Kenneth Casson Leighton lkcl@lkcl.net wrote:
[...]
You may be thinking of a different couple of orders of magnitude less than the task I have in mind, here David. I am designing a quad core 800mhz design with L1/L2 cache, multi issue out of order vector processing, virtual memory and 16, 32 and 64 bit IEEE754 FP units (we may also add FP8, have to see).
Performance target is 4 32bit FP FMACs per core per cycle, so a total of at least 16 FMAC ALUs, potentially double that, to minimise data routing (a trick I learned on comp.arch: ALUs are cheap, data routing horribly expensive).
I am NOT going to throw such a massively complex design at an autorouter and hope for the best. It would be flat out insane to consider.
The hybrid hierarchical approach would allow the autorouter to lay out an FPU FMAC cell, that, on successful completion, can be incorporated into a larger ALU cell (per core), that in turn may be incorporated into a CPU Cell, that in turn may be incorporated into an SoC final layout.
Each time *using* the autorouter however NOT repeat NOT to allow it to REDO cells that have already been done: ONLY allow it to place and route them.
Restricting and simplifying the scope of work needed to be done by SEVERAL orders of magnitude.
In this way I stand a chance of having a complete design in a sane amount of time.
ok, so what is the transistor feature size, and the required reliability and repeatability of transistor parameters in the CMOS process that supports a design of such scale?
Followup question to the foundry alchemists: Do you think you stand a chance to implement a process with such small feature sizes and such tight specifications in a sane amount of time?
Irrespective of that, it always makes sense to select or write design tools that don't run into some "640k ought to be enough for anybody" barrier.
- tatzelbrumm