[Libre-silicon-devel] Finally! Solved the issue with spacers and silicide

Hi all I've you have a look into the document, I've just pushed the results from my research into the topic of how to reduce the poly/dran/gate resistance. I've also cracked the problem of how to etch spacers. Can you folks think of any more test structures for the test-section besides plain NMOS/PMOS and different caps and resistors using all the different layers? Cheers David