Hi
Also did you check Tile-Link/Chip-Link?
Well, here is what I've looked at so far: * AXI is backed by a lot of patents backed by US companies. I've picked out two[1][2] of the many many patents out there. * Wishbone from OpenCores – Free and open bus architecture (formerly from Silicore[6]) * CoreConnect bus technology from IBM, used in IBM's embedded Power Architecture products, but also in many other SoC-like systems with the Xilinx MicroBlaze or similar cores. Which means it's even more evil than AXI * IPBus by IDT (Patents ole!) * Avalon – proprietary bus system by Altera for use in their Nios II SoCs[5] * Open Core Protocol (OCP) from Accellera * HyperTransport (HT) from AMD (though this is an off-chip interface, not on chip bus) * QuickPath Interconnect (QPI) by Intel (though this is an off-chip interface, not on chip bus) * virtual share from PICC - free and open source However, a Google search didn't spit out useful information. Apparently it's not so popular * Tile-Link/Chip-Link[3] [4] doesn't seem to have been patented yet and seems to come from universities and the like. Apparently SiFive have been thinking the same thing we've been thinking.
Candidates now are: * Wishbone * Tile Link * PICC
I'm open for suggestions where we should go from here. I'd say we should rather use TileLink, because there is already support for it in rocket-core. We can just throw out AXI4 and have no potential patent issues anymore
Cheers David
[1] https://patents.google.com/patent/US7069376B2 [2] https://patents.google.com/patent/US20050138253 [3] https://bar.eecs.berkeley.edu/projects/tilelink.html [4] https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf [5] http://www.altera.com/literature/manual/mnl_avalon_spec.pdf [6] http://www.pldworld.com/_hdl/2/_ip/-silicore.net/wishpats.htm